SlaveAxiLiteIpIntegrator Entity Reference

Inheritance diagram for SlaveAxiLiteIpIntegrator:

Collaboration diagram for SlaveAxiLiteIpIntegrator:

Entities
SlaveAxiLiteIpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
INTERFACENAME	string := " S_AXI "
EN_ERROR_RESP	boolean := false
HAS_PROT	natural range 0 to 1 := 0
HAS_WSTRB	natural range 0 to 1 := 0
FREQ_HZ	positive := 100000000
ADDR_WIDTH	positive := 12

Ports
S_AXI_ACLK	in	std_logic
S_AXI_ARESETN	in	std_logic
S_AXI_AWADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_AWVALID	in	std_logic
S_AXI_AWREADY	out	std_logic
S_AXI_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXI_WVALID	in	std_logic
S_AXI_WREADY	out	std_logic
S_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out	std_logic
S_AXI_BREADY	in	std_logic
S_AXI_ARADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_ARVALID	in	std_logic
S_AXI_ARREADY	out	std_logic
S_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out	std_logic
S_AXI_RREADY	in	std_logic
axilClk	out	sl
axilRst	out	sl
axilReadMaster	out	AxiLiteReadMasterType
axilReadSlave	in	AxiLiteReadSlaveType
axilWriteMaster	out	AxiLiteWriteMasterType
axilWriteSlave	in	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd
• build/SRC_VHDL/surf/SlaveAxiLiteIpIntegrator.vhd