Architecture >> SlaveAxiLiteIpIntegrator::mapping

Signals
S_AXI_ReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
S_AXI_ReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
S_AXI_WriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
S_AXI_WriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Attributes
X_INTERFACE_INFO	string
X_INTERFACE_PARAMETER	string
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RRESP "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RDATA "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARADDR "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARPROT "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " BREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " BVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " BRESP "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WDATA "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WSTRB "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWPROT "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWADDR "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME " & INTERFACENAME& " , " & " PROTOCOL AXI4LITE , " & " DATA_WIDTH 32 , " & " HAS_PROT " & integer ' image ( HAS_PROT ) & " , " & " HAS_WSTRB " & integer ' image ( HAS_WSTRB ) & " , " & " MAX_BURST_LENGTH 1 , " & " ADDR_WIDTH " & integer ' image ( ADDR_WIDTH ) & " , " & " FREQ_HZ " & integer ' image ( FREQ_HZ )
X_INTERFACE_INFO	signal is " xilinx.com : signal : reset : 1.0 RST. " & INTERFACENAME& " _ARESETN RST "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME RST. " & INTERFACENAME& " _ARESETN , " & " POLARITY ACTIVE_LOW "
X_INTERFACE_INFO	signal is " xilinx.com : signal : clock : 1.0 CLK. " & INTERFACENAME& " _ACLK CLK "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME CLK. " & INTERFACENAME& " _ACLK , " & " ASSOCIATED_BUSIF " & INTERFACENAME& " , " & " ASSOCIATED_RESET " & INTERFACENAME& " _ARESETN , " & " FREQ_HZ " & integer ' image ( FREQ_HZ )

Instantiations
u_rstsync	RstSync <Entity RstSync>
u_rstsync	RstSync <Entity RstSync>

The documentation for this design unit was generated from the following files:

axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd
build/SRC_VHDL/surf/SlaveAxiLiteIpIntegrator.vhd

Signals

Attributes

Instantiations