FirFilterMultiChannel Entity Reference

Inheritance diagram for FirFilterMultiChannel:

Collaboration diagram for FirFilterMultiChannel:

Entities
FirFilterMultiChannel.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
NUM_TAPS_G	positive
NUM_CHANNELS_G	positive
PARALLEL_G	positive
DATA_WIDTH_G	positive
COEFF_WIDTH_G	positive range 1 to 32
COEFFICIENTS_G	IntegerArray := ( 0 = > 0 )
MEMORY_TYPE_G	string := " distributed "
SYNTH_MODE_G	string := " inferred "

Ports
axisClk	in	sl
axisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• dsp/generic/fixed/FirFilterMultiChannel.vhd