Architecture >> FirFilterMultiChannel::mapping

Processes
comb	( axiWrAddr , axiWrValid , axisRst , cascout , mAxisSlave , r , sAxisMaster )
seq	( axisClk )
GLUE	( cascCache , cascout , sAxisMaster )

Constants
WORDS_PER_FRAME_C	positive := NUM_CHANNELS_G/ PARALLEL_G
CASC_RAM_ADDR_WIDTH_C	positive := bitSize ( WORDS_PER_FRAME_C- 1 )
CASC_WIDTH_C	integer := COEFF_WIDTH_G+ DATA_WIDTH_G+ log2 ( NUM_TAPS_G )
CASC_RAM_DATA_WIDTH_C	*integer := CASC_WIDTH_C NUM_TAPS_G* PARALLEL_G**
COEF_RAM_DATA_WIDTH_C	*integer := COEFF_WIDTH_G NUM_TAPS_G**
COEFF_RAM_ADDR_WIDTH_G	integer := bitSize ( NUM_TAPS_G- 1 )
COEFFICIENTS_C	CoeffArray := initCoeffArray
REG_INIT_C	RegType := ( ramWe = > ' 0 ' , addr = > ( others = > ' 0 ' ) , coeffin = > COEFFICIENTS_C , coeffce = > ( others = > ' 0 ' ) , sAxisSlave = > AXI_STREAM_SLAVE_INIT_C , axisMeta = > AXI_STREAM_MASTER_INIT_C , mAxisMaster = > AXI_STREAM_MASTER_INIT_C )

Types
DataArray	( PARALLEL_G- 1 downto 0 ) slv ( DATA_WIDTH_G- 1 downto 0 )
CascArray	( NUM_TAPS_G- 1 downto 0 , PARALLEL_G- 1 downto 0 ) slv ( CASC_WIDTH_C- 1 downto 0 )
CoeffArray	( NUM_TAPS_G- 1 downto 0 ) slv ( COEFF_WIDTH_G- 1 downto 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType
datain	DataArray
cascEn	sl
cascin	CascArray
cascout	CascArray
cascCache	CascArray
ramWe	sl
raddr	slv ( CASC_RAM_ADDR_WIDTH_C- 1 downto 0 )
waddr	slv ( CASC_RAM_ADDR_WIDTH_C- 1 downto 0 )
ramDin	slv ( CASC_RAM_DATA_WIDTH_C- 1 downto 0 )
ramDout	slv ( CASC_RAM_DATA_WIDTH_C- 1 downto 0 )
axiWrValid	sl := ' 0 '
axiWrAddr	slv ( COEFF_RAM_ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
axiWrData	slv ( 31 downto 0 ) := ( others = > ' 0 ' )

Records
RegType

Instantiations
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>
u_cache	DualPortRam <Entity DualPortRam>
u_tap	FirFilterTap <Entity FirFilterTap>

The documentation for this design unit was generated from the following file:

Functions

Processes