FirFilterTap Entity Reference

Inheritance diagram for FirFilterTap:

Entities
FirFilterTap.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
DATA_WIDTH_G	positive := 12
COEFF_WIDTH_G	positive := 12
COEFF_INIT_G	slv := X " 000 "
CASC_WIDTH_G	positive := 25

Ports
clk	in	sl
en	in	sl := ' 1 '
datain	in	slv ( DATA_WIDTH_G- 1 downto 0 )
coeffin	in	slv ( COEFF_WIDTH_G- 1 downto 0 )
coeffce	in	sl
cascin	in	slv ( CASC_WIDTH_G- 1 downto 0 )
cascout	out	slv ( CASC_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/FirFilterTap.vhd
• dsp/generic/fixed/FirFilterTap.vhd