FirFilterTap.rtl Architecture Reference

Architecture >> FirFilterTap::rtl

Processes
comb	( cascin , coeffce , coeffin , datain , en , r )
seq	( clk )
comb	( cascin , coeffce , coeffin , datain , en , r )
seq	( clk )

Constants
PROD_WIDTH_C	integer := DATA_WIDTH_G+ COEFF_WIDTH_G
COEFF_INIT_C	slv ( COEFF_WIDTH_G- 1 downto 0 ) := resize ( COEFF_INIT_G , COEFF_WIDTH_G )
REG_INIT_C	RegType := ( accum = > ( others = > ' 0 ' ) , coeff = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/FirFilterTap.vhd
• dsp/generic/fixed/FirFilterTap.vhd