ClinkUart.rtl Architecture Reference

Architecture >> ClinkUart::rtl

Processes
comb	( baud , intRst , r )
seq	( intClk )
PROCESS_243	( rdData , rdValid )

Constants
INT_FREQ_C	integer := 200000000
INT_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 4 , tDestBits = > 0 )
REG_INIT_C	RegType := ( count = > 0 , baudClkEn = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
rdData	slv ( 7 downto 0 )
rdValid	sl
txMasters	AxiStreamMasterArray ( 1 downto 0 )
txSlaves	AxiStreamSlaveArray ( 1 downto 0 )
rxMaster	AxiStreamMasterType

Records
RegType

Instantiations
u_txfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_txthrottle	ClinkUartThrottle <Entity ClinkUartThrottle>
u_uarttx_1	UartTx <Entity UartTx>
u_uartrx_1	UartRx <Entity UartRx>
u_rxfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following file:

• protocols/clink/rtl/ClinkUart.vhd