UartRx Entity Reference

Inheritance diagram for UartRx:

Collaboration diagram for UartRx:

Entities
UartRx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
PARITY_G	string := " NONE "
BAUD_MULT_G	integer range 2 to 16 := 16
DATA_WIDTH_G	integer range 5 to 8 := 8

Ports
clk	in	sl
rst	in	sl
baudClkEn	in	sl
rdData	out	slv ( DATA_WIDTH_G- 1 downto 0 )
rdValid	out	sl
parityError	out	sl
rdReady	in	sl
rx	in	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartRx.vhd
• protocols/uart/rtl/UartRx.vhd