UartRx.rtl Architecture Reference

Architecture >> UartRx::rtl

Processes
comb	( baudClkEn , r , rdReady , rst , rxFall , rxSync )
sync	( clk )
comb	( baudClkEn , r , rdReady , rst , rxFall , rxSync )
sync	( clk )

Constants
REG_INIT_C	RegType := ( rdValid = > ' 0 ' , rdData = > ( others = > ' 0 ' ) , rxState = > WAIT_START_BIT_S , waitState = > SAMPLE_RX_S , rxShiftReg = > ( others = > ' 0 ' ) , rxShiftCount = > ( others = > ' 0 ' ) , baudClkEnCount = > ( others = > ' 0 ' ) , parity = > ' 0 ' , parityError = > ' 0 ' )

Types
StateType	( WAIT_START_BIT_S , WAIT_HALF_S , WAIT_FULL_S , SAMPLE_RX_S , PARITY_S , WAIT_STOP_S , WRITE_OUT_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rxSync	sl
rxFall	sl

Records
RegType

Instantiations
u_synchronizeredge_1	SynchronizerEdge <Entity SynchronizerEdge>
u_synchronizeredge_1	SynchronizerEdge <Entity SynchronizerEdge>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartRx.vhd
• protocols/uart/rtl/UartRx.vhd