UartTx Entity Reference

Inheritance diagram for UartTx:

Entities
UartTx.RTL	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
STOP_BITS_G	integer range 1 to 2 := 1
PARITY_G	string := " NONE "
BAUD_MULT_G	integer range 2 to 16 := 16
DATA_WIDTH_G	integer range 5 to 8 := 8

Ports
clk	in	sl
rst	in	sl
baudClkEn	in	sl
wrData	in	slv ( DATA_WIDTH_G- 1 downto 0 )
wrValid	in	sl
wrReady	out	sl
tx	out	sl

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartTx.vhd
• protocols/uart/rtl/UartTx.vhd