UartTx.RTL Architecture Reference

Architecture >> UartTx::RTL

Processes
comb	( baudClkEn , r , rst , wrData , wrValid )
seq	( clk )
comb	( baudClkEn , r , rst , wrData , wrValid )
seq	( clk )

Constants
PARITY_BITS_C	integer := ite ( PARITY_G = " NONE " , 0 , 1 )
START_BIT_C	integer := 1
SHIFT_REG_WIDTH_C	integer := START_BIT_C+ DATA_WIDTH_G+ PARITY_BITS_C+ STOP_BITS_G
REG_INIT_C	RegType := ( wrReady = > ' 0 ' , holdReg = > ( others = > ' 0 ' ) , parity = > ' 0 ' , txState = > WAIT_DATA_S , baudClkEnCount = > ( others = > ' 0 ' ) , shiftReg = > ( others = > ' 1 ' ) , shiftCount = > ( others = > ' 0 ' ) )

Types
StateType	( WAIT_DATA_S , SYNC_EN_S , WAIT_S , TX_BIT_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartTx.vhd
• protocols/uart/rtl/UartTx.vhd