Architecture >> AxiStreamMuxTb::testbed

Processes
rearb_proc	( fastClk )
PROCESS_8	( fastClk )
PROCESS_9	( failedFast , failedSlow , passedSlow )
PROCESS_10	( slowClk )
rearb_proc	( fastClk )
PROCESS_89	( fastClk )
PROCESS_90	( failedFast , failedSlow , passedSlow )
PROCESS_91	( slowClk )

Constants
SLOW_CLK_PERIOD_C	time := 10 ns
FAST_CLK_PERIOD_C	time := SLOW_CLK_PERIOD_C/ 3 . 14159
TPD_C	time := FAST_CLK_PERIOD_C/ 4
STATUS_CNT_WIDTH_C	natural := 32
TX_PACKET_LENGTH_C	slv ( 31 downto 0 ) := toSlv ( 32 , 32 )
NUMBER_PACKET_C	slv ( 31 downto 0 ) := toSlv ( 4096 , 32 )
MUX_SIZE_C	natural := 4
MEMORY_TYPE_G	string := " block "
CASCADE_SIZE_C	natural := 1
FIFO_ADDR_WIDTH_C	natural := 9
FIFO_PAUSE_THRESH_C	natural := 2 8**
PRBS_SEED_SIZE_C	natural := 32
PRBS_TAPS_C	NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
AXI_STREAM_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
AXI_PIPE_STAGES_C	natural := 1

Signals
fastClk	sl := ' 0 '
fastRst	sl := ' 1 '
slowClk	sl := ' 0 '
slowRst	sl := ' 1 '
dropWrite	sl := ' 0 '
dropFrame	sl := ' 0 '
passedSlow	slv ( MUX_SIZE_C- 1 downto 0 ) := ( others = > ' 0 ' )
failedSlow	sl := ' 0 '
failedFast	sl := ' 0 '
updated	slv ( MUX_SIZE_C- 1 downto 0 ) := ( others = > ' 0 ' )
errorDet	slv ( MUX_SIZE_C- 1 downto 0 ) := ( others = > ' 0 ' )
errLength	sl := ' 0 '
errDataBus	sl := ' 0 '
errEofe	sl := ' 0 '
errWordCnt	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
errbitCnt	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt	Slv32Array ( MUX_SIZE_C- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
packetLengths	Slv32Array ( MUX_SIZE_C- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
ibMaster	AxiStreamMasterType
ibSlave	AxiStreamSlaveType
ibMasters	AxiStreamMasterArray ( MUX_SIZE_C- 1 downto 0 )
ibSlaves	AxiStreamSlaveArray ( MUX_SIZE_C- 1 downto 0 )
obMaster	AxiStreamMasterType
obSlave	AxiStreamSlaveType
obMasters	AxiStreamMasterArray ( MUX_SIZE_C- 1 downto 0 )
obSlaves	AxiStreamSlaveArray ( MUX_SIZE_C- 1 downto 0 )
rearbitrate	sl := ' 0 '
rearbCount	integer := 0

Instantiations
clkrst_fast	ClkRst <Entity ClkRst>
clkrst_slow	ClkRst <Entity ClkRst>
ssiprbstx_inst	SsiPrbsTx <Entity SsiPrbsTx>
u_axistreammux	AxiStreamMux <Entity AxiStreamMux>
u_axistreamdemux	AxiStreamDeMux <Entity AxiStreamDeMux>
ssiprbsrx_inst	SsiPrbsRx <Entity SsiPrbsRx>
clkrst_fast	ClkRst <Entity ClkRst>
clkrst_slow	ClkRst <Entity ClkRst>
ssiprbstx_inst	SsiPrbsTx <Entity SsiPrbsTx>
u_axistreammux	AxiStreamMux <Entity AxiStreamMux>
u_axistreamdemux	AxiStreamDeMux <Entity AxiStreamDeMux>
ssiprbsrx_inst	SsiPrbsRx <Entity SsiPrbsRx>

The documentation for this design unit was generated from the following files:

Processes

Constants