AxiStreamDmaV2.structure Architecture Reference

Architecture >> AxiStreamDmaV2::structure

Signals
dmaWrDescReq	AxiWriteDmaDescReqArray ( CHAN_COUNT_G- 1 downto 0 )
dmaWrDescAck	AxiWriteDmaDescAckArray ( CHAN_COUNT_G- 1 downto 0 )
dmaWrDescRet	AxiWriteDmaDescRetArray ( CHAN_COUNT_G- 1 downto 0 )
dmaWrDescRetAck	slv ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescReq	AxiReadDmaDescReqArray ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescAck	slv ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescRet	AxiReadDmaDescRetArray ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescRetAck	slv ( CHAN_COUNT_G- 1 downto 0 )
descWriteMasters	AxiWriteMasterArray ( CHAN_COUNT_G- 1 downto 0 )
descWriteSlaves	AxiWriteSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
dataWriteMasters	AxiWriteMasterArray ( CHAN_COUNT_G- 1 downto 0 )
dataWriteSlaves	AxiWriteSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
dataWriteCtrl	AxiCtrlArray ( CHAN_COUNT_G- 1 downto 0 )
axiRdCache	slv ( 3 downto 0 )
axiWrCache	slv ( 3 downto 0 )
axiReset	slv ( CHAN_COUNT_G- 1 downto 0 )

Attributes
dont_touch	string
dont_touch	signal is " true "

Instantiations
u_dmadesc	AxiStreamDmaV2Desc <Entity AxiStreamDmaV2Desc>
u_axisrst	RstPipeline <Entity RstPipeline>
u_dmaread	AxiStreamDmaV2Read <Entity AxiStreamDmaV2Read>
u_dmawrite	AxiStreamDmaV2Write <Entity AxiStreamDmaV2Write>
u_dmawritemux	AxiStreamDmaV2WriteMux <Entity AxiStreamDmaV2WriteMux>
u_dmadesc	AxiStreamDmaV2Desc <Entity AxiStreamDmaV2Desc>
u_axisrst	RstPipeline <Entity RstPipeline>
u_dmaread	AxiStreamDmaV2Read <Entity AxiStreamDmaV2Read>
u_dmawrite	AxiStreamDmaV2Write <Entity AxiStreamDmaV2Write>
u_dmawritemux	AxiStreamDmaV2WriteMux <Entity AxiStreamDmaV2WriteMux>

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2.vhd