AxiStreamDmaV2Write Entity Reference

Inheritance diagram for AxiStreamDmaV2Write:

Collaboration diagram for AxiStreamDmaV2Write:

Entities
AxiStreamDmaV2Write.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns
AXI_READY_EN_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType
AXI_CONFIG_G	AxiConfigType
PIPE_STAGES_G	natural := 1
BURST_BYTES_G	integer range 1 to 4096 := 4096
ACK_WAIT_BVALID_G	boolean := true

Ports
axiClk	in	sl
axiRst	in	sl
dmaWrDescReq	out	AxiWriteDmaDescReqType
dmaWrDescAck	in	AxiWriteDmaDescAckType
dmaWrDescRet	out	AxiWriteDmaDescRetType
dmaWrDescRetAck	in	sl
dmaWrIdle	out	sl
axiCache	in	slv ( 3 downto 0 )
axisMaster	in	AxiStreamMasterType
axisSlave	out	AxiStreamSlaveType
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
axiWriteCtrl	in	AxiCtrlType := AXI_CTRL_UNUSED_C

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2Write.vhd