Architecture >> AxiStreamDmaV2Write::rtl

Processes
comb	( axiCache , axiRst , axiWriteSlave , dmaWrDescAck , dmaWrDescRetAck , intAxisMaster , pause , r , trackData )
seq	( axiClk )
comb	( axiCache , axiRst , axiWriteSlave , dmaWrDescAck , dmaWrDescRetAck , intAxisMaster , pause , r , trackData )
seq	( axiClk )

Constants
DATA_BYTES_C	integer := AXIS_CONFIG_G.TDATA_BYTES_C
ADDR_LSB_C	integer := bitSize ( DATA_BYTES_C- 1 )
FIFO_ADDR_WIDTH_C	natural := ( AXI_CONFIG_G.LEN_BITS_C+ 1 )
REG_INIT_C	RegType := ( dmaWrDescReq = > AXI_WRITE_DMA_DESC_REQ_INIT_C , dmaWrTrack = > AXI_WRITE_DMA_TRACK_INIT_C , dmaWrDescRet = > AXI_WRITE_DMA_DESC_RET_INIT_C , result = > ( others = > ' 0 ' ) , reqCount = > ( others = > ' 0 ' ) , ackCount = > ( others = > ' 0 ' ) , stCount = > ( others = > ' 0 ' ) , timeoutCnt = > ( others = > ' 0 ' ) , awlen = > ( others = > ' 0 ' ) , axiLen = > AXI_LEN_INIT_C , wMaster = > axiWriteMasterInit ( AXI_CONFIG_G , ' 1 ' , " 01 " , " 0000 " ) , slave = > AXI_STREAM_SLAVE_INIT_C , state = > RESET_S , lastUser = > ( others = > ' 0 ' ) , continue = > ' 0 ' , dmaWrIdle = > ' 0 ' )

Types
StateType	( RESET_S , INIT_S , IDLE_S , REQ_S , ADDR_S , MOVE_S , PAD_S , META_S , RETURN_S , DUMP_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
pause	sl
intAxisMaster	AxiStreamMasterType
intAxisSlave	AxiStreamSlaveType
trackDin	slv ( AXI_WRITE_DMA_TRACK_SIZE_C- 1 downto 0 )
trackDout	slv ( AXI_WRITE_DMA_TRACK_SIZE_C- 1 downto 0 )
trackData	AxiWriteDmaTrackType

Records
RegType

Instantiations
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_trackram	DualPortRam <Entity DualPortRam>
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_trackram	DualPortRam <Entity DualPortRam>

The documentation for this design unit was generated from the following files:

Processes

Constants