AxiStreamDmaV2 Entity Reference

Inheritance diagram for AxiStreamDmaV2:

Collaboration diagram for AxiStreamDmaV2:

Entities
AxiStreamDmaV2.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
DESC_AWIDTH_G	positive range 4 to 12 := 12
DESC_ARB_G	boolean := true
DESC_SYNTH_MODE_G	string := " inferred "
DESC_MEMORY_TYPE_G	string := " block "
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := x " 00000000 "
AXI_READY_EN_G	boolean := false
AXIS_READY_EN_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType
AXI_DMA_CONFIG_G	AxiConfigType
CHAN_COUNT_G	positive range 1 to 16 := 1
BURST_BYTES_G	positive range 1 to 4096 := 4096
WR_PIPE_STAGES_G	natural := 1
RD_PIPE_STAGES_G	natural := 1
RD_PEND_THRESH_G	positive := 1

Ports
axiClk	in	sl
axiRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
interrupt	out	sl
online	out	slv ( CHAN_COUNT_G- 1 downto 0 )
acknowledge	out	slv ( CHAN_COUNT_G- 1 downto 0 )
buffGrpPause	out	slv ( 7 downto 0 )
sAxisMasters	in	AxiStreamMasterArray ( CHAN_COUNT_G- 1 downto 0 )
sAxisSlaves	out	AxiStreamSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
mAxisMasters	out	AxiStreamMasterArray ( CHAN_COUNT_G- 1 downto 0 )
mAxisSlaves	in	AxiStreamSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
mAxisCtrl	in	AxiStreamCtrlArray ( CHAN_COUNT_G- 1 downto 0 )
axiReadMasters	out	AxiReadMasterArray ( CHAN_COUNT_G downto 0 )
axiReadSlaves	in	AxiReadSlaveArray ( CHAN_COUNT_G downto 0 )
axiWriteMasters	out	AxiWriteMasterArray ( CHAN_COUNT_G downto 0 )
axiWriteSlaves	in	AxiWriteSlaveArray ( CHAN_COUNT_G downto 0 )
axiWriteCtrl	in	AxiCtrlArray ( CHAN_COUNT_G downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2.vhd