AxiStreamDmaV2Desc Entity Reference

Inheritance diagram for AxiStreamDmaV2Desc:

Collaboration diagram for AxiStreamDmaV2Desc:

Entities
AxiStreamDmaV2Desc.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiDmaPkg	Package <AxiDmaPkg>
ArbiterPkg	Package <ArbiterPkg>

Generics
TPD_G	time := 1 ns
CHAN_COUNT_G	integer range 1 to 16 := 1
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := x " 00000000 "
AXI_CONFIG_G	AxiConfigType
DESC_AWIDTH_G	integer range 4 to 32 := 12
DESC_ARB_G	boolean := true
DESC_SYNTH_MODE_G	string := " inferred "
DESC_MEMORY_TYPE_G	string := " block "

Ports
axiClk	in	sl
axiRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
interrupt	out	sl
online	out	slv ( CHAN_COUNT_G- 1 downto 0 )
acknowledge	out	slv ( CHAN_COUNT_G- 1 downto 0 )
dmaWrDescReq	in	AxiWriteDmaDescReqArray ( CHAN_COUNT_G- 1 downto 0 )
dmaWrDescAck	out	AxiWriteDmaDescAckArray ( CHAN_COUNT_G- 1 downto 0 )
dmaWrDescRet	in	AxiWriteDmaDescRetArray ( CHAN_COUNT_G- 1 downto 0 )
dmaWrDescRetAck	out	slv ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescReq	out	AxiReadDmaDescReqArray ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescAck	in	slv ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescRet	in	AxiReadDmaDescRetArray ( CHAN_COUNT_G- 1 downto 0 )
dmaRdDescRetAck	out	slv ( CHAN_COUNT_G- 1 downto 0 )
axiRdCache	out	slv ( 3 downto 0 )
axiWrCache	out	slv ( 3 downto 0 )
axiWriteMasters	out	AxiWriteMasterArray ( CHAN_COUNT_G- 1 downto 0 )
axiWriteSlaves	in	AxiWriteSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
buffGrpPause	out	slv ( 7 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2Desc.vhd