AxiStreamDmaV2Desc.rtl Architecture Reference

Architecture >> AxiStreamDmaV2Desc::rtl

Processes
comb	( axiRst , axiWriteSlaves , axilReadMaster , axilWriteMaster , diffCnt , dmaRdDescAck , dmaRdDescRet , dmaWrDescReq , dmaWrDescRet , holdoffCompare , idBuffCompare , intSwAckEn , invalidCount , r , rdFifoDout , rdFifoValid , wrFifoDout , wrFifoValid )
seq	( axiClk )
comb	( axiRst , axiWriteSlaves , axilReadMaster , axilWriteMaster , diffCnt , dmaRdDescAck , dmaRdDescRet , dmaWrDescReq , dmaWrDescRet , holdoffCompare , idBuffCompare , intSwAckEn , invalidCount , r , rdFifoDout , rdFifoValid , wrFifoDout , wrFifoValid )
seq	( axiClk )

Constants
AXI_DESC_CONFIG_C	AxiConfigType := ( ADDR_WIDTH_C = > AXI_CONFIG_G.ADDR_WIDTH_C , DATA_BYTES_C = > 16 , ID_BITS_C = > AXI_CONFIG_G.ID_BITS_C , LEN_BITS_C = > AXI_CONFIG_G.LEN_BITS_C )
CHAN_SIZE_C	integer := bitSize ( CHAN_COUNT_G- 1 )
RET_COUNT_C	integer := CHAN_COUNT_G* 2
RET_SIZE_C	integer := bitSize ( RET_COUNT_C- 1 )
RD_FIFO_CNT_C	integer := 4
RD_FIFO_BITS_C	integer := RD_FIFO_CNT_C* 32
WR_FIFO_CNT_C	integer := 2
WR_FIFO_BITS_C	integer := WR_FIFO_CNT_C* 32
REG_INIT_C	RegType := ( dmaWrDescAck = > ( others = > AXI_WRITE_DMA_DESC_ACK_INIT_C ) , dmaWrDescRetAck = > ( others = > ' 0 ' ) , dmaRdDescReq = > ( others = > AXI_READ_DMA_DESC_REQ_INIT_C ) , dmaRdDescRetAck = > ( others = > ' 0 ' ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axiWriteMaster = > axiWriteMasterInit ( AXI_DESC_CONFIG_C , ' 1 ' , " 01 " , " 0000 " ) , wrBaseAddr = > ( others = > ' 0 ' ) , rdBaseAddr = > ( others = > ' 0 ' ) , maxSize = > ( others = > ' 0 ' ) , contEn = > ' 0 ' , dropEn = > ' 0 ' , enable = > ' 0 ' , forceInt = > ' 0 ' , intEnable = > ' 0 ' , online = > ( others = > ' 0 ' ) , acknowledge = > ( others = > ' 0 ' ) , fifoReset = > ' 1 ' , intSwAckReq = > ' 0 ' , intAckCount = > ( others = > ' 0 ' ) , descWrCache = > ( others = > ' 0 ' ) , buffRdCache = > ( others = > ' 0 ' ) , buffWrCache = > ( others = > ' 0 ' ) , enableCnt = > ( others = > ' 0 ' ) , idBuffThold = > ( others = > ( others = > ' 0 ' ) ) , wrTimeout = > x " 0000FFFF " , fifoDin = > ( others = > ' 0 ' ) , wrFifoWr = > ( others = > ' 0 ' ) , rdFifoWr = > ( others = > ' 0 ' ) , addrFifoSel = > ' 0 ' , wrFifoRd = > ' 0 ' , wrFifoValidDly = > ( others = > ' 0 ' ) , wrAddrValid = > ' 0 ' , rdFifoRd = > ' 0 ' , rdFifoValidDly = > ( others = > ' 0 ' ) , rdAddrValid = > ' 0 ' , wrReqValid = > ' 0 ' , wrReqCnt = > 0 , wrReqNum = > ( others = > ' 0 ' ) , wrReqAcks = > ( others = > ' 0 ' ) , wrReqMissed = > ( others = > ' 0 ' ) , descRetList = > ( others = > ' 0 ' ) , descState = > IDLE_S , descRetCnt = > 0 , descRetNum = > ( others = > ' 0 ' ) , descRetAcks = > ( others = > ' 0 ' ) , wrIndex = > ( others = > ' 0 ' ) , wrMemAddr = > ( others = > ' 0 ' ) , rdIndex = > ( others = > ' 0 ' ) , rdMemAddr = > ( others = > ' 0 ' ) , intReqEn = > ' 0 ' , intReqCount = > ( others = > ' 0 ' ) , interrupt = > ' 0 ' , intHoldoff = > toSlv ( 10000 , 16 ) , intHoldoffCount = > ( others = > ' 0 ' ) , idBuffCount = > ( others = > ( others = > ' 0 ' ) ) , idBuffInc = > ( others = > ' 0 ' ) , idBuffDec = > ( others = > ' 0 ' ) , buffGrpPause = > ( others = > ' 0 ' ) )

Types
DescStateType	( IDLE_S , WRITE_S , READ_S , WAIT_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rdFifoValid	slv ( RD_FIFO_CNT_C- 1 downto 0 )
rdFifoDout	slv ( RD_FIFO_BITS_C- 1 downto 0 )
wrFifoValid	slv ( WR_FIFO_CNT_C- 1 downto 0 )
wrFifoDout	slv ( WR_FIFO_BITS_C- 1 downto 0 )
intSwAckEn	sl
intCompValid	sl
intDiffValid	sl
invalidCount	sl
diffCnt	slv ( 31 downto 0 )
holdoffCompare	sl
idBuffCompare	slv ( 7 downto 0 )

Records
RegType

Instantiations
u_descfifo	Fifo <Entity Fifo>
u_rdfifo	Fifo <Entity Fifo>
u_invalidcount	DspComparator <Entity DspComparator>
u_diffcnt	DspAddSub <Entity DspAddSub>
u_holdoffcompare	DspComparator <Entity DspComparator>
u_dspcomparator	DspComparator <Entity DspComparator>
u_descfifo	Fifo <Entity Fifo>
u_rdfifo	Fifo <Entity Fifo>
u_invalidcount	DspComparator <Entity DspComparator>
u_diffcnt	DspAddSub <Entity DspAddSub>
u_holdoffcompare	DspComparator <Entity DspComparator>
u_dspcomparator	DspComparator <Entity DspComparator>

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2Desc.vhd