AxiStreamDmaV2Read Entity Reference

Inheritance diagram for AxiStreamDmaV2Read:

Collaboration diagram for AxiStreamDmaV2Read:

Entities
AxiStreamDmaV2Read.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns
AXIS_READY_EN_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType
AXI_CONFIG_G	AxiConfigType
PIPE_STAGES_G	natural := 1
BURST_BYTES_G	positive range 1 to 4096 := 4096
PEND_THRESH_G	positive := 1

Ports
axiClk	in	sl
axiRst	in	sl
dmaRdDescReq	in	AxiReadDmaDescReqType
dmaRdDescAck	out	sl
dmaRdDescRet	out	AxiReadDmaDescRetType
dmaRdDescRetAck	in	sl
dmaRdIdle	out	sl
axiCache	in	slv ( 3 downto 0 )
axisMaster	out	AxiStreamMasterType
axisSlave	in	AxiStreamSlaveType
axisCtrl	in	AxiStreamCtrlType
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2Read.vhd