AxiStreamDmaV2Read.rtl Architecture Reference

Architecture >> AxiStreamDmaV2Read::rtl

Processes
comb	( axiCache , axiReadSlave , axiRst , dmaRdDescReq , dmaRdDescRetAck , notReqDone , pause , r , sSlave )
seq	( axiClk )
comb	( axiCache , axiReadSlave , axiRst , dmaRdDescReq , dmaRdDescRetAck , notReqDone , pause , r , sSlave )
seq	( axiClk )

Constants
DATA_BYTES_C	positive := AXIS_CONFIG_G.TDATA_BYTES_C
ADDR_LSB_C	natural := ite ( ( DATA_BYTES_C = 1 ) , 0 , bitSize ( DATA_BYTES_C- 1 ) )
PEND_LSB_C	natural := bitSize ( PEND_THRESH_G- 1 )
REG_INIT_C	RegType := ( idle = > ' 0 ' , pending = > true , size = > ( others = > ' 0 ' ) , reqSize = > ( others = > ' 0 ' ) , reqCnt = > ( others = > ' 0 ' ) , ackCnt = > ( others = > ' 0 ' ) , dmaRdDescReq = > AXI_READ_DMA_DESC_REQ_INIT_C , dmaRdDescAck = > ' 0 ' , dmaRdDescRet = > AXI_READ_DMA_DESC_RET_INIT_C , first = > ' 0 ' , leftovers = > ' 0 ' , axiLen = > AXI_LEN_INIT_C , rMaster = > axiReadMasterInit ( AXI_CONFIG_G , " 01 " , " 0000 " ) , sMaster = > axiStreamMasterInit ( AXIS_CONFIG_G ) , reqState = > IDLE_S , state = > IDLE_S )

Types
ReqStateType	( IDLE_S , NEXT_S , ADDR_S , DLY_S )
StateType	( IDLE_S , MOVE_S , DONE_S , BLOWOFF_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
pause	sl
notReqDone	sl
sSlave	AxiStreamSlaveType
mSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_dspcomparator	DspComparator <Entity DspComparator>
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_dspcomparator	DspComparator <Entity DspComparator>
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2Read.vhd