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AxiStreamDmaV2WriteMux Entity Reference
Inheritance diagram for AxiStreamDmaV2WriteMux:Entities | |
| AxiStreamDmaV2WriteMux.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiPkg | Package <AxiPkg> |
Generics | |
| TPD_G | time := 1 ns |
| AXI_CONFIG_G | AxiConfigType |
| AXI_READY_EN_G | boolean := false |
| ACK_WAIT_BVALID_G | boolean := false |
Ports | ||
| axiClk | in | sl |
| axiRst | in | sl |
| dataWriteMaster | in | AxiWriteMasterType |
| dataWriteSlave | out | AxiWriteSlaveType |
| dataWriteCtrl | out | AxiCtrlType |
| descWriteMaster | in | AxiWriteMasterType |
| descWriteSlave | out | AxiWriteSlaveType |
| mAxiWriteMaster | out | AxiWriteMasterType |
| mAxiWriteSlave | in | AxiWriteSlaveType |
| mAxiWriteCtrl | in | AxiCtrlType |
The documentation for this design unit was generated from the following file:
- axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd
