AxiStreamDmaV2WriteMux.rtl Architecture Reference

Architecture >> AxiStreamDmaV2WriteMux::rtl

Processes
comb	( axiRst , dataWriteMaster , descWriteMaster , mAxiWriteCtrl , mAxiWriteSlave , r )
seq	( axiClk )
comb	( axiRst , dataWriteMaster , descWriteMaster , mAxiWriteCtrl , mAxiWriteSlave , r )
seq	( axiClk )

Constants
REG_INIT_C	RegType := ( pause = > ' 0 ' , armed = > ' 0 ' , descSlave = > AXI_WRITE_SLAVE_INIT_C , dataSlave = > AXI_WRITE_SLAVE_INIT_C , descriptor = > AXI_WRITE_MASTER_INIT_C , master = > AXI_WRITE_MASTER_INIT_C , state = > ADDR_S )

Types
StateType	( ADDR_S , DATA_S , DESC_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

---

The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2WriteMux.vhd