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AxiStreamDmaV2FifoIpIntegrator.rtl Architecture Reference
Architecture >> AxiStreamDmaV2FifoIpIntegrator::rtl

Constants

AXIS_CONFIG_C  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
AXI_CONFIG_C  AxiConfigType := axiConfig ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > 4 , ID_BITS_C = > 8 , LEN_BITS_C = > 8 )

Signals

axiResetN  sl := ' 1 '
axilResetN  sl := ' 1 '
mAxiAwLock  slv ( 1 downto 0 ) := ( others = > ' 0 ' )
mAxiArLock  slv ( 1 downto 0 ) := ( others = > ' 0 ' )
axilReadMaster  AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave  AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster  AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave  AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
sAxisCtrl  AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C
mAxisMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
axiReadMaster  AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave  AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
axiWriteMaster  AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave  AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C

Instantiations

u_axil  SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_s_axis  SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_m_axis  MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_m_axi  MasterAxiIpIntegrator <Entity MasterAxiIpIntegrator>
u_dut  AxiStreamDmaV2Fifo <Entity AxiStreamDmaV2Fifo>

The documentation for this design unit was generated from the following file: