AxiStreamDmaV2Fifo Entity Reference

Inheritance diagram for AxiStreamDmaV2Fifo:

Collaboration diagram for AxiStreamDmaV2Fifo:

Entities
AxiStreamDmaV2Fifo.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
BUFF_FRAME_WIDTH_G	positive := 20
AXI_BUFFER_WIDTH_G	positive := 30
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
AXIS_CONFIG_G	AxiStreamConfigType
AXI_BASE_ADDR_G	slv ( 63 downto 0 ) := x " 0000_0000_0000_0000 "
AXI_CONFIG_G	AxiConfigType
AXI_BURST_G	slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G	slv ( 3 downto 0 ) := " 1111 "
BURST_BYTES_G	positive range 1 to 4096 := 4096
RD_PEND_THRESH_G	positive := 1

Ports
axiClk	in	sl
axiRst	in	sl
axiReady	in	sl
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
sAxisCtrl	out	AxiStreamCtrlType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2Fifo.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2Fifo.vhd