AxiStreamDmaV2Fifo.rtl Architecture Reference

Architecture >> AxiStreamDmaV2Fifo::rtl

Functions
slv	localToSlv ( r: in AxiReadDmaDescReqType )
AxiReadDmaDescReqType	localToAxiReadDmaDescReq ( din: in slv , valid: in sl )
slv	localToSlv ( r: in AxiReadDmaDescReqType )
AxiReadDmaDescReqType	localToAxiReadDmaDescReq ( din: in slv , valid: in sl )

Processes
comb	( axiReady , axiRst , dmaRdDescRet , dmaRdIdle , dmaWrDescReq , dmaWrDescRet , r , rdBuffCnt , rdQueueData , rdQueueValid , regReadMaster , regWriteMaster , wrBuffCnt , wrIndex , wrIndexValid )
seq	( axiClk )
comb	( axiReady , axiRst , dmaRdDescRet , dmaRdIdle , dmaWrDescReq , dmaWrDescRet , r , rdBuffCnt , rdQueueData , rdQueueValid , regReadMaster , regWriteMaster , wrBuffCnt , wrIndex , wrIndexValid )
seq	( axiClk )

Constants
ADDR_WIDTH_C	positive := AXI_BUFFER_WIDTH_G- BUFF_FRAME_WIDTH_G
RD_QUEUE_WIDTH_C	positive := ADDR_WIDTH_C+ 1 + ( BUFF_FRAME_WIDTH_G+ 1 ) + ( 2 * AXIS_CONFIG_G.TUSER_BITS_C ) + AXIS_CONFIG_G.TDEST_BITS_C+ AXIS_CONFIG_G.TID_BITS_C
REG_INIT_C	RegType := ( reset = > ' 1 ' , rstCnt = > ' 0 ' , wrIndexValid = > ' 0 ' , wrIndexReady = > ' 0 ' , wrIndex = > ( others = > ' 1 ' ) , dmaWrDescAck = > AXI_WRITE_DMA_DESC_ACK_INIT_C , dmaWrDescRetAck = > ' 0 ' , rdQueueValid = > ' 0 ' , rdQueueReady = > ' 0 ' , rdQueueData = > ( others = > ' 0 ' ) , dmaRdDescReq = > AXI_READ_DMA_DESC_REQ_INIT_C , dmaRdDescRetAck = > ' 0 ' , sAxisCtrl = > AXI_STREAM_CTRL_INIT_C , pauseThresh = > toSlv ( 2 ** ( ADDR_WIDTH_C- 1 ) , ADDR_WIDTH_C ) , pauseCnt = > ( others = > ' 0 ' ) , regReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , regWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , txnLatecy = > ( others = > ( others = > ' 0 ' ) ) , state = > RESET_S )

Types
StateType	( RESET_S , INIT_S , IDLE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
dmaWrDescReq	AxiWriteDmaDescReqType
dmaWrDescAck	AxiWriteDmaDescAckType
dmaWrDescRet	AxiWriteDmaDescRetType
dmaWrDescRetAck	sl
dmaRdDescReq	AxiReadDmaDescReqType
dmaRdDescAck	sl
dmaRdDescRet	AxiReadDmaDescRetType
dmaRdDescRetAck	sl
dmaRdIdle	sl
wrBuffCnt	slv ( ADDR_WIDTH_C- 1 downto 0 )
wrIndex	slv ( ADDR_WIDTH_C- 1 downto 0 )
wrIndexValid	sl
wrIndexReady	sl
rdBuffCnt	slv ( ADDR_WIDTH_C- 1 downto 0 )
rdQueueData	slv ( RD_QUEUE_WIDTH_C- 1 downto 0 )
rdQueueValid	sl
rdQueueReady	sl
regReadMaster	AxiLiteReadMasterType
regReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
regWriteMaster	AxiLiteWriteMasterType
regWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

Records
RegType

Instantiations
u_ibdma	AxiStreamDmaV2Write <Entity AxiStreamDmaV2Write>
u_obdma	AxiStreamDmaV2Read <Entity AxiStreamDmaV2Read>
u_writequeue	Fifo <Entity Fifo>
u_readqueue	Fifo <Entity Fifo>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_ibdma	AxiStreamDmaV2Write <Entity AxiStreamDmaV2Write>
u_obdma	AxiStreamDmaV2Read <Entity AxiStreamDmaV2Read>
u_writequeue	Fifo <Entity Fifo>
u_readqueue	Fifo <Entity Fifo>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v2/AxiStreamDmaV2Fifo.vhd
• build/SRC_VHDL/surf/AxiStreamDmaV2Fifo.vhd