AxiStreamDmaV2FifoIpIntegrator Entity Reference

Inheritance diagram for AxiStreamDmaV2FifoIpIntegrator:

Collaboration diagram for AxiStreamDmaV2FifoIpIntegrator:

Entities
AxiStreamDmaV2FifoIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns

Ports
axiClk	in	sl
axiRst	in	sl
axilClk	in	sl
axilRst	in	sl
axiReady	in	sl
sAxisPause	out	sl
sAxisOverflow	out	sl
sAxisIdle	out	sl
S_AXI_AWADDR	in	slv ( 7 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( 7 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl
S_AXIS_TVALID	in	sl
S_AXIS_TDATA	in	slv ( 31 downto 0 )
S_AXIS_TKEEP	in	slv ( 3 downto 0 )
S_AXIS_TLAST	in	sl
S_AXIS_TDEST	in	slv ( 7 downto 0 )
S_AXIS_TID	in	slv ( 7 downto 0 )
S_AXIS_TUSER	in	slv ( 1 downto 0 )
S_AXIS_TREADY	out	sl
M_AXIS_TVALID	out	sl
M_AXIS_TDATA	out	slv ( 31 downto 0 )
M_AXIS_TKEEP	out	slv ( 3 downto 0 )
M_AXIS_TLAST	out	sl
M_AXIS_TDEST	out	slv ( 7 downto 0 )
M_AXIS_TID	out	slv ( 7 downto 0 )
M_AXIS_TUSER	out	slv ( 1 downto 0 )
M_AXIS_TREADY	in	sl
M_AXI_AWID	out	slv ( 7 downto 0 )
M_AXI_AWADDR	out	slv ( 15 downto 0 )
M_AXI_AWLEN	out	slv ( 7 downto 0 )
M_AXI_AWSIZE	out	slv ( 2 downto 0 )
M_AXI_AWBURST	out	slv ( 1 downto 0 )
M_AXI_AWLOCK	out	sl
M_AXI_AWCACHE	out	slv ( 3 downto 0 )
M_AXI_AWPROT	out	slv ( 2 downto 0 )
M_AXI_AWREGION	out	slv ( 3 downto 0 )
M_AXI_AWQOS	out	slv ( 3 downto 0 )
M_AXI_AWVALID	out	sl
M_AXI_AWREADY	in	sl
M_AXI_WID	out	slv ( 7 downto 0 )
M_AXI_WDATA	out	slv ( 31 downto 0 )
M_AXI_WSTRB	out	slv ( 3 downto 0 )
M_AXI_WLAST	out	sl
M_AXI_WVALID	out	sl
M_AXI_WREADY	in	sl
M_AXI_BID	in	slv ( 7 downto 0 )
M_AXI_BRESP	in	slv ( 1 downto 0 )
M_AXI_BVALID	in	sl
M_AXI_BREADY	out	sl
M_AXI_ARID	out	slv ( 7 downto 0 )
M_AXI_ARADDR	out	slv ( 15 downto 0 )
M_AXI_ARLEN	out	slv ( 7 downto 0 )
M_AXI_ARSIZE	out	slv ( 2 downto 0 )
M_AXI_ARBURST	out	slv ( 1 downto 0 )
M_AXI_ARLOCK	out	sl
M_AXI_ARCACHE	out	slv ( 3 downto 0 )
M_AXI_ARPROT	out	slv ( 2 downto 0 )
M_AXI_ARREGION	out	slv ( 3 downto 0 )
M_AXI_ARQOS	out	slv ( 3 downto 0 )
M_AXI_ARVALID	out	sl
M_AXI_ARREADY	in	sl
M_AXI_RID	in	slv ( 7 downto 0 )
M_AXI_RDATA	in	slv ( 31 downto 0 )
M_AXI_RRESP	in	slv ( 1 downto 0 )
M_AXI_RLAST	in	sl
M_AXI_RVALID	in	sl
M_AXI_RREADY	out	sl

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd