AxiStreamDemuxMuxTb.mapping Architecture Reference

Architecture >> AxiStreamDemuxMuxTb::mapping

Signals
axisClk	sl := ' 0 '
axisRst	sl := ' 0 '
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
axisMasters	AxiStreamMasterArray ( MUX_STREAMS_G- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
axisSlaves	AxiStreamSlaveArray ( MUX_STREAMS_G- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C )
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Instantiations
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_demux	AxiStreamDeMux <Entity AxiStreamDeMux>
u_mux	AxiStreamMux <Entity AxiStreamMux>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_demux	AxiStreamDeMux <Entity AxiStreamDeMux>
u_mux	AxiStreamMux <Entity AxiStreamMux>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd
• build/SRC_VHDL/surf/AxiStreamDemuxMuxTb.vhd