AxiStreamDemuxMuxTb Entity Reference

Inheritance diagram for AxiStreamDemuxMuxTb:

Collaboration diagram for AxiStreamDemuxMuxTb:

Entities
AxiStreamDemuxMuxTb.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TUSER_WIDTH_G	positive range 1 to 8 := 1
TID_WIDTH_G	positive range 1 to 8 := 1
TDEST_WIDTH_G	positive range 1 to 8 := 1
TDATA_NUM_BYTES_G	positive range 1 to 128 := 1
MUX_STREAMS_G	positive := 2
PIPE_STAGES_G	natural := 0
ILEAVE_EN_G	boolean := false
ILEAVE_ON_NOTVALID_G	boolean := false
ILEAVE_REARB_G	natural := 0
REARB_DELAY_G	boolean := true
FORCED_REARB_HOLD_G	boolean := false

Ports
AXIS_ACLK	in	std_logic := ' 0 '
AXIS_ARESETN	in	std_logic := ' 0 '
S_AXIS_TVALID	in	std_logic := ' 0 '
S_AXIS_TDATA	in	std_logic_vector ( ( 8 * TDATA_NUM_BYTES_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TSTRB	in	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TKEEP	in	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TLAST	in	std_logic := ' 0 '
S_AXIS_TDEST	in	std_logic_vector ( TDEST_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TID	in	std_logic_vector ( TID_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TUSER	in	std_logic_vector ( TUSER_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TREADY	out	std_logic
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( ( 8 * TDATA_NUM_BYTES_G ) - 1 downto 0 )
M_AXIS_TSTRB	out	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TDEST	out	std_logic_vector ( TDEST_WIDTH_G- 1 downto 0 )
M_AXIS_TID	out	std_logic_vector ( TID_WIDTH_G- 1 downto 0 )
M_AXIS_TUSER	out	std_logic_vector ( TUSER_WIDTH_G- 1 downto 0 )
M_AXIS_TREADY	in	std_logic

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd
• build/SRC_VHDL/surf/AxiStreamDemuxMuxTb.vhd