Architecture >> Ad9681ReadoutManual::rtl

Processes
axilComb	( adcFrameSync , axilR , axilReadMaster , axilRst , axilWriteMaster , curDelayData , curDelayFrame , debugDataTmp , debugDataValid , lockedFallCount , lockedSync )
axilSeq	( axilClk )
adcComb	( adcFrame , adcR , relockSync )
adcSeq	( adcBitClkR , adcBitRst )
GLUE_COMB	( adcData , adcValid , invertSync , negateSync )

Constants
NUM_CHANNELS_C	natural := 8
AXIL_REG_INIT_C	AxilRegType := ( axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , delay = > toSlv ( DEFAULT_DELAY_G , 5 ) , dataDelaySet = > ( others = > ( others = > ' 1 ' ) ) , frameDelaySet = > " 11 " , freezeDebug = > ' 0 ' , readoutDebug0 = > ( others = > ( others = > ' 0 ' ) ) , readoutDebug1 = > ( others = > ( others = > ' 0 ' ) ) , lockedCountRst = > ' 0 ' , invert = > toSl ( INVERT_G ) , negate = > toSl ( NEGATE_G ) , relock = > " 00 " , curDelayFrame = > ( others = > ( others = > ' 0 ' ) ) , curDelayData = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) )
ADC_REG_INIT_C	AdcRegType := ( state = > RESET_S , slip = > ' 0 ' , count = > ( others = > ' 0 ' ) , locked = > ' 0 ' , reset = > ' 1 ' )

Types
AdcDataArray	array ( natural range <> ) of slv8Array ( 7 downto 0 )
DelayDataArray	array ( natural range <> ) of slv5Array ( 7 downto 0 )
SyncStateType	( RESET_S , SYNCING_S , SYNCED_S )
AdcRegArray	array ( natural range <> ) of AdcRegType

Signals
lockedSync	slv ( 1 downto 0 )
lockedFallCount	slv16Array ( 1 downto 0 )
axilR	AxilRegType := AXIL_REG_INIT_C
axilRin	AxilRegType
adcR	AdcRegArray ( 1 downto 0 ) := ( others = > ADC_REG_INIT_C )
adcRin	AdcRegArray ( 1 downto 0 )
adcValid	slv ( 1 downto 0 )
tmpAdcClk	slv ( 1 downto 0 )
adcBitClkIo	slv ( 1 downto 0 )
adcBitClkIoInv	slv ( 1 downto 0 )
adcBitClkR	slv ( 1 downto 0 )
adcBitRst	slv ( 1 downto 0 )
adcFramePad	slv ( 1 downto 0 )
adcFrame	slv8Array ( 1 downto 0 )
adcFrameSync	slv8Array ( 1 downto 0 )
adcDataPad	slv8Array ( 1 downto 0 )
adcData	AdcDataArray ( 1 downto 0 )
curDelayFrame	slv5Array ( 1 downto 0 )
curDelayData	DelayDataArray ( 1 downto 0 )
fifoWrData	slv16Array ( NUM_CHANNELS_C- 1 downto 0 )
fifoDataValid	sl
fifoDataOut	*slv ( NUM_CHANNELS_C 16 - 1 downto 0 )**
fifoDataIn	*slv ( NUM_CHANNELS_C 16 - 1 downto 0 )**
fifoDataTmp	slv16Array ( NUM_CHANNELS_C- 1 downto 0 )
debugDataValid	sl
debugDataOut	*slv ( NUM_CHANNELS_C 16 - 1 downto 0 )**
debugDataTmp	slv16Array ( NUM_CHANNELS_C- 1 downto 0 )
invertSync	slv ( 1 downto 0 )
negateSync	slv ( 1 downto 0 )
relockSync	slv ( 1 downto 0 )

Instantiations
synchronizeroneshotcnt_1	SynchronizerOneShotCnt <Entity SynchronizerOneShotCnt>
synchronizer_1	Synchronizer <Entity Synchronizer>
synchronizervec_1	SynchronizerVector <Entity SynchronizerVector>
synchronizer_2	Synchronizer <Entity Synchronizer>
synchronizer_4	Synchronizer <Entity Synchronizer>
synchronizer_3	Synchronizer <Entity Synchronizer>
adcclk_i_ibufds	ibufds
u_bufio	bufio
u_adcbitclkr	bufr
adc_bitclk_rst_sync	RstSync <Entity RstSync>
u_framein	ibufds
u_frame_deserializer	Ad9681Deserializer <Entity Ad9681Deserializer>
u_datain	ibufds
u_data_deserializer	Ad9681Deserializer <Entity Ad9681Deserializer>
u_datafifo	SynchronizerFifo <Entity SynchronizerFifo>
u_datafifodebug	SynchronizerFifo <Entity SynchronizerFifo>

The documentation for this design unit was generated from the following file:

Processes

Constants