SURF  1.0
UartWrapper.vhd
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1 -------------------------------------------------------------------------------
2 -- File : UartAxiLiteMaster.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2016-06-09
5 -- Last update: 2016-06-09
6 -------------------------------------------------------------------------------
7 -- Description: Ties together everything needed for a full duplex UART.
8 -- This includes Baud Rate Generator, Transmitter, Receiver and FIFOs.
9 -------------------------------------------------------------------------------
10 -- This file is part of 'SLAC Firmware Standard Library'.
11 -- It is subject to the license terms in the LICENSE.txt file found in the
12 -- top-level directory of this distribution and at:
13 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
14 -- No part of 'SLAC Firmware Standard Library', including this file,
15 -- may be copied, modified, propagated, or distributed except according to
16 -- the terms contained in the LICENSE.txt file.
17 -------------------------------------------------------------------------------
18 
19 library ieee;
20 use ieee.std_logic_1164.all;
21 use ieee.std_logic_arith.all;
22 use ieee.std_logic_unsigned.all;
23 
24 use work.StdRtlPkg.all;
25 
26 --! @see entity
27  --! @ingroup protocols_uart
28 entity UartWrapper is
29 
30  generic (
31  TPD_G : time := 1 ns;
32  CLK_FREQ_G : real := 125.0e6;
33  BAUD_RATE_G : integer := 115200;
34  FIFO_BRAM_EN_G : boolean := false;
35  FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 4);
36  port (
37  clk : in sl;
38  rst : in sl;
39  -- Transmit parallel interface
40  wrData : in slv(7 downto 0);
41  wrValid : in sl;
42  wrReady : out sl;
43  -- Receive parallel interface
44  rdData : out slv(7 downto 0);
45  rdValid : out sl;
46  rdReady : in sl;
47  -- Serial IO
48  tx : out sl;
49  rx : in sl);
50 
51 end entity UartWrapper;
52 
53 architecture rtl of UartWrapper is
54 
55  signal uartTxData : slv(7 downto 0);
56  signal uartTxValid : sl;
57  signal uartTxReady : sl;
58  signal uartTxRdEn : sl;
59  signal fifoTxData : slv(7 downto 0);
60  signal fifoTxValid : sl;
61  signal fifoTxReady : sl;
62 
63  signal uartRxData : slv(7 downto 0);
64  signal uartRxValid : sl;
65  signal uartRxValidInt : sl;
66  signal uartRxReady : sl;
67  signal fifoRxData : slv(7 downto 0);
68  signal fifoRxValid : sl;
69  signal fifoRxReady : sl;
70  signal fifoRxRdEn : sl;
71 
72  signal baud16x : sl;
73 
74 begin
75 
76  -------------------------------------------------------------------------------------------------
77  -- Tie parallel IO to internal signals
78  -------------------------------------------------------------------------------------------------
79 
80 
81  -------------------------------------------------------------------------------------------------
82  -- Baud Rate Generator.
83  -- Create a clock enable that is 16x the baud rate.
84  -- UartTx and UartRx use this.
85  -------------------------------------------------------------------------------------------------
86  U_UartBrg_1 : entity work.UartBrg
87  generic map (
88  CLK_FREQ_G => CLK_FREQ_G,
89  BAUD_RATE_G => BAUD_RATE_G,
90  MULTIPLIER_G => 16)
91  port map (
92  clk => clk, -- [in]
93  rst => rst, -- [in]
94  clkEn => baud16x); -- [out]
95 
96  -------------------------------------------------------------------------------------------------
97  -- UART transmitter
98  -------------------------------------------------------------------------------------------------
99  U_UartTx_1 : entity work.UartTx
100  generic map (
101  TPD_G => TPD_G)
102  port map (
103  clk => clk, -- [in]
104  rst => rst, -- [in]
105  baud16x => baud16x, -- [in]
106  wrData => uartTxData, -- [in]
107  wrValid => uartTxValid, -- [in]
108  wrReady => uartTxReady, -- [out]
109  tx => tx); -- [out]
110 
111  -------------------------------------------------------------------------------------------------
112  -- FIFO to feed UART transmitter
113  -------------------------------------------------------------------------------------------------
114  wrReady <= fifoTxReady;
115  fifoTxData <= wrData;
116  fifoTxValid <= wrValid and fifoTxReady;
117  uartTxRdEn <= uartTxReady and uartTxValid;
118  U_Fifo_Tx : entity work.Fifo
119  generic map (
120  TPD_G => TPD_G,
121  GEN_SYNC_FIFO_G => true,
122  BRAM_EN_G => FIFO_BRAM_EN_G,
123  FWFT_EN_G => true,
124  PIPE_STAGES_G => 0,
125  DATA_WIDTH_G => 8,
126  ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G)
127  port map (
128  rst => rst, -- [in]
129  wr_clk => clk, -- [in]
130  wr_en => fifoTxValid, -- [in]
131  din => fifoTxData, -- [in]
132  not_full => fifoTxReady, -- [out]
133  rd_clk => clk, -- [in]
134  rd_en => uartTxRdEn, -- [in]
135  dout => uartTxData, -- [out]
136  valid => uartTxValid); -- [out]
137 
138  -------------------------------------------------------------------------------------------------
139  -- UART Receiver
140  -------------------------------------------------------------------------------------------------
141  U_UartRx_1 : entity work.UartRx
142  generic map (
143  TPD_G => TPD_G)
144  port map (
145  clk => clk, -- [in]
146  rst => rst, -- [in]
147  baud16x => baud16x, -- [in]
148  rdData => uartRxData, -- [out]
149  rdValid => uartRxValid, -- [out]
150  rdReady => uartRxReady, -- [in]
151  rx => rx); -- [in]
152 
153  -------------------------------------------------------------------------------------------------
154  -- FIFO for UART Received data
155  -------------------------------------------------------------------------------------------------
156  fifoRxRdEn <= fifoRxReady and fifoRxValid;
157  uartRxValidInt <= uartRxValid and uartRxReady;
158 
159  rdData <= fifoRxData;
160  rdValid <= fifoRxValid;
161  fifoRxReady <= rdReady;
162 
163  U_Fifo_Rx : entity work.Fifo
164  generic map (
165  TPD_G => TPD_G,
166  GEN_SYNC_FIFO_G => true,
167  BRAM_EN_G => FIFO_BRAM_EN_G,
168  FWFT_EN_G => true,
169  PIPE_STAGES_G => 0,
170  DATA_WIDTH_G => 8,
171  ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G)
172  port map (
173  rst => rst, -- [in]
174  wr_clk => clk, -- [in]
175  wr_en => uartRxValidInt, -- [in]
176  din => uartRxData, -- [in]
177  not_full => uartRxReady, -- [out]
178  rd_clk => clk, -- [in]
179  rd_en => fifoRxRdEn, -- [in]
180  dout => fifoRxData, -- [out]
181  valid => fifoRxValid); -- [out]
182 
183 end architecture rtl;
Fifo.din
in dinslv( DATA_WIDTH_G- 1 downto 0)
Definition: Fifo.vhd:52
UartTx.wrData
in wrDataslv( 7 downto 0)
Definition: UartTx.vhd:33
UartTx.TPD_G
TPD_Gtime := 1 ns
Definition: UartTx.vhd:28
UartWrapper.wrValid
in wrValidsl
Definition: UartWrapper.vhd:41
UartTx.wrValid
in wrValidsl
Definition: UartTx.vhd:34
UartRx.rdReady
in rdReadysl
Definition: UartRx.vhd:35
UartRx.rx
in rxsl
Definition: UartRx.vhd:36
UartWrapper.FIFO_ADDR_WIDTH_G
FIFO_ADDR_WIDTH_Ginteger range 4 to 48:= 4
Definition: UartWrapper.vhd:35
Fifo.BRAM_EN_G
BRAM_EN_Gboolean := true
Definition: Fifo.vhd:32
UartBrg.rst
in rstsl
Definition: UartBrg.vhd:33
UartRx.TPD_G
TPD_Gtime := 1 ns
Definition: UartRx.vhd:28
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
Fifo.FWFT_EN_G
FWFT_EN_Gboolean := false
Definition: Fifo.vhd:33
UartWrapper.wrData
in wrDataslv( 7 downto 0)
Definition: UartWrapper.vhd:40
UartBrg.clk
in clksl
Definition: UartBrg.vhd:32
UartWrapper.rdReady
in rdReadysl
Definition: UartWrapper.vhd:46
Fifo.rd_clk
in rd_clksl
Definition: Fifo.vhd:61
Fifo.TPD_G
TPD_Gtime := 1 ns
Definition: Fifo.vhd:28
UartBrg.clkEn
out clkEnsl
Definition: UartBrg.vhd:34
UartWrapper.rdData
out rdDataslv( 7 downto 0)
Definition: UartWrapper.vhd:44
UartRx.rdData
out rdDataslv( 7 downto 0)
Definition: UartRx.vhd:33
Fifo.DATA_WIDTH_G
DATA_WIDTH_Ginteger range 1 to ( 2** 24):= 16
Definition: Fifo.vhd:41
Fifo.wr_clk
in wr_clksl
Definition: Fifo.vhd:50
UartWrapper.wrReady
out wrReadysl
Definition: UartWrapper.vhd:42
UartWrapper.rdValid
out rdValidsl
Definition: UartWrapper.vhd:45
UartWrapper.BAUD_RATE_G
BAUD_RATE_Ginteger := 115200
Definition: UartWrapper.vhd:33
Fifo.valid
out validsl
Definition: Fifo.vhd:65
UartWrapper.TPD_G
TPD_Gtime := 1 ns
Definition: UartWrapper.vhd:31
Fifo.rd_en
in rd_ensl := '0'
Definition: Fifo.vhd:62
UartWrapper.FIFO_BRAM_EN_G
FIFO_BRAM_EN_Gboolean := false
Definition: UartWrapper.vhd:34
UartTx.tx
out txsl
Definition: UartTx.vhd:36
UartTx.wrReady
out wrReadysl
Definition: UartTx.vhd:35
Fifo.GEN_SYNC_FIFO_G
GEN_SYNC_FIFO_Gboolean := false
Definition: Fifo.vhd:31
Fifo.not_full
out not_fullsl
Definition: Fifo.vhd:59
UartWrapper.CLK_FREQ_G
CLK_FREQ_Greal := 125.0e6
Definition: UartWrapper.vhd:32
UartRx.rst
in rstsl
Definition: UartRx.vhd:31
UartBrg.BAUD_RATE_G
BAUD_RATE_Ginteger := 115200
Definition: UartBrg.vhd:29
UartRx.rdValid
out rdValidsl
Definition: UartRx.vhd:34
Fifo.dout
out doutslv( DATA_WIDTH_G- 1 downto 0)
Definition: Fifo.vhd:63
Fifo.rst
in rstsl :=not RST_POLARITY_G
Definition: Fifo.vhd:48
Fifo.PIPE_STAGES_G
PIPE_STAGES_Gnatural range 0 to 16:= 0
Definition: Fifo.vhd:40
UartRx.clk
in clksl
Definition: UartRx.vhd:30
Fifo.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger range 4 to 48:= 4
Definition: Fifo.vhd:42
UartBrg.CLK_FREQ_G
CLK_FREQ_Greal := 125.0E6
Definition: UartBrg.vhd:28
UartTx.baud16x
in baud16xsl
Definition: UartTx.vhd:32
UartTx.rst
in rstsl
Definition: UartTx.vhd:31
UartBrg.MULTIPLIER_G
MULTIPLIER_Ginteger := 16
Definition: UartBrg.vhd:30
UartTx.clk
in clksl
Definition: UartTx.vhd:30
UartRx.baud16x
in baud16xsl
Definition: UartRx.vhd:32
Fifo
Definition: Fifo.vhd:26
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
Fifo.wr_en
in wr_ensl := '0'
Definition: Fifo.vhd:51