surf_1_documentation/html/Fifo_8vhd_source.html

 -------------------------------------------------------------------------------
 -- File       : Fifo.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2013-07-14
 -- Last update: 2014-05-05
 -------------------------------------------------------------------------------
 -- Description: FIFO Wrapper
 -------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
 -- It is subject to the license terms in the LICENSE.txt file found in the
 -- top-level directory of this distribution and at:
 --    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
 -- No part of 'SLAC Firmware Standard Library', including this file,
 -- may be copied, modified, propagated, or distributed except according to
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 use work.StdRtlPkg.all;

 --! @see entity
  --! @ingroup base_fifo
 entity Fifo is
    generic (
       TPD_G           : time                       := 1 ns;
       RST_POLARITY_G  : sl                         := '1';  -- '1' for active high rst, '0' for active low
       RST_ASYNC_G     : boolean                    := false;
       GEN_SYNC_FIFO_G : boolean                    := false;
       BRAM_EN_G       : boolean                    := true;
       FWFT_EN_G       : boolean                    := false;
       USE_DSP48_G     : string                     := "no";
       ALTERA_SYN_G    : boolean                    := false;
       ALTERA_RAM_G    : string                     := "M9K";
       USE_BUILT_IN_G  : boolean                    := false;  --if set to true, this module is only xilinx compatible only!!!
       XIL_DEVICE_G    : string                     := "7SERIES";  --xilinx only generic parameter
       SYNC_STAGES_G   : integer range 3 to (2**24) := 3;
       PIPE_STAGES_G   : natural range 0 to 16      := 0;
       DATA_WIDTH_G    : integer range 1 to (2**24) := 16;
       ADDR_WIDTH_G    : integer range 4 to 48      := 4;
       INIT_G          : slv                        := "0";
       FULL_THRES_G    : integer range 1 to (2**24) := 1;
       EMPTY_THRES_G   : integer range 1 to (2**24) := 1);
    port (
       -- Resets
       rst           : in  sl := not RST_POLARITY_G;
       --Write Ports (wr_clk domain)
       wr_clk        : in  sl;
       wr_en         : in  sl := '0';
       din           : in  slv(DATA_WIDTH_G-1 downto 0);
       wr_data_count : out slv(ADDR_WIDTH_G-1 downto 0);
       wr_ack        : out sl;
       overflow      : out sl;
       prog_full     : out sl;
       almost_full   : out sl;
       full          : out sl;
       not_full      : out sl;
       --Read Ports (rd_clk domain)
       rd_clk        : in  sl;           --unused if GEN_SYNC_FIFO_G = true
       rd_en         : in  sl := '0';
       dout          : out slv(DATA_WIDTH_G-1 downto 0);
       rd_data_count : out slv(ADDR_WIDTH_G-1 downto 0);
       valid         : out sl;
       underflow     : out sl;
       prog_empty    : out sl;
       almost_empty  : out sl;
       empty         : out sl);
 end Fifo;

 architecture rtl of Fifo is

    constant INIT_C   : slv(DATA_WIDTH_G-1 downto 0) := ite(INIT_G = "0", slvZero(DATA_WIDTH_G), INIT_G);
    signal data_count : slv(ADDR_WIDTH_G-1 downto 0) := (others => '0');

 begin

    assert (INIT_G = "0" or INIT_G'length = DATA_WIDTH_G) report
       "INIT_G must either be ""0"" or the same length as DATA_WIDTH_G" severity failure;

    NON_BUILT_IN_GEN : if (USE_BUILT_IN_G = false) generate
       FIFO_ASYNC_Gen : if (GEN_SYNC_FIFO_G = false) generate
          FifoAsync_Inst : entity work.FifoAsync
             generic map (
                TPD_G          => TPD_G,
                RST_POLARITY_G => RST_POLARITY_G,
                BRAM_EN_G      => BRAM_EN_G,
                FWFT_EN_G      => FWFT_EN_G,
                USE_DSP48_G    => USE_DSP48_G,
                ALTERA_SYN_G   => ALTERA_SYN_G,
                ALTERA_RAM_G   => ALTERA_RAM_G,
                SYNC_STAGES_G  => SYNC_STAGES_G,
                PIPE_STAGES_G  => PIPE_STAGES_G,
                DATA_WIDTH_G   => DATA_WIDTH_G,
                ADDR_WIDTH_G   => ADDR_WIDTH_G,
                INIT_G         => INIT_C,
                FULL_THRES_G   => FULL_THRES_G,
                EMPTY_THRES_G  => EMPTY_THRES_G)
             port map (
                rst           => rst,
                wr_clk        => wr_clk,
                wr_en         => wr_en,
                din           => din,
                wr_data_count => wr_data_count,
                wr_ack        => wr_ack,
                overflow      => overflow,
                prog_full     => prog_full,
                almost_full   => almost_full,
                full          => full,
                not_full      => not_full,
                rd_clk        => rd_clk,
                rd_en         => rd_en,
                dout          => dout,
                rd_data_count => rd_data_count,
                valid         => valid,
                underflow     => underflow,
                prog_empty    => prog_empty,
                almost_empty  => almost_empty,
                empty         => empty);
       end generate;

       FIFO_SYNC_Gen : if (GEN_SYNC_FIFO_G = true) generate
          wr_data_count <= data_count;
          rd_data_count <= data_count;

          FifoSync_Inst : entity work.FifoSync
             generic map (
                TPD_G          => TPD_G,
                RST_POLARITY_G => RST_POLARITY_G,
                RST_ASYNC_G    => RST_ASYNC_G,
                BRAM_EN_G      => BRAM_EN_G,
                FWFT_EN_G      => FWFT_EN_G,
                USE_DSP48_G    => USE_DSP48_G,
                ALTERA_RAM_G   => ALTERA_RAM_G,
                PIPE_STAGES_G  => PIPE_STAGES_G,
                DATA_WIDTH_G   => DATA_WIDTH_G,
                ADDR_WIDTH_G   => ADDR_WIDTH_G,
                INIT_G         => INIT_C,
                FULL_THRES_G   => FULL_THRES_G,
                EMPTY_THRES_G  => EMPTY_THRES_G)
             port map (
                rst          => rst,
                clk          => wr_clk,
                wr_en        => wr_en,
                rd_en        => rd_en,
                din          => din,
                dout         => dout,
                data_count   => data_count,
                wr_ack       => wr_ack,
                valid        => valid,
                overflow     => overflow,
                underflow    => underflow,
                prog_full    => prog_full,
                prog_empty   => prog_empty,
                almost_full  => almost_full,
                almost_empty => almost_empty,
                full         => full,
                not_full     => not_full,
                empty        => empty);
       --NOTE:
       --    When mapping the FifoSync, I am assuming that
       --    wr_clk = rd_clk (both in frequency and in phase)
       --    and I only pass wr_clk into the FifoSync_Inst
       end generate;
    end generate;

    BUILT_IN_GEN : if (USE_BUILT_IN_G = true) generate
       FIFO_SYNC_BUILT_IN_GEN : if (GEN_SYNC_FIFO_G = true) generate
          wr_data_count <= data_count;
          rd_data_count <= data_count;

          FifoSyncBuiltIn_Inst : entity work.FifoSyncBuiltIn
             generic map (
                TPD_G          => TPD_G,
                RST_POLARITY_G => RST_POLARITY_G,
                XIL_DEVICE_G   => XIL_DEVICE_G,
                USE_DSP48_G    => USE_DSP48_G,
                FWFT_EN_G      => FWFT_EN_G,
                PIPE_STAGES_G  => PIPE_STAGES_G,
                DATA_WIDTH_G   => DATA_WIDTH_G,
                ADDR_WIDTH_G   => ADDR_WIDTH_G,
                FULL_THRES_G   => FULL_THRES_G,
                EMPTY_THRES_G  => EMPTY_THRES_G)
             port map (
                rst          => rst,
                clk          => wr_clk,
                wr_en        => wr_en,
                rd_en        => rd_en,
                din          => din,
                dout         => dout,
                data_count   => data_count,
                wr_ack       => wr_ack,
                valid        => valid,
                overflow     => overflow,
                underflow    => underflow,
                prog_full    => prog_full,
                prog_empty   => prog_empty,
                almost_full  => almost_full,
                almost_empty => almost_empty,
                full         => full,
                not_full     => not_full,
                empty        => empty);
       --NOTE:
       --    When mapping the FifoSync, I am assuming that
       --    wr_clk = rd_clk (both in frequency and in phase)
       --    and I only pass wr_clk into the FifoSyncBuiltIn_Inst
       end generate;
       FIFO_ASYNC_BUILT_IN_GEN : if (GEN_SYNC_FIFO_G = false) generate
          FifoAsyncBuiltIn_Inst : entity work.FifoAsyncBuiltIn
             generic map (
                TPD_G          => TPD_G,
                RST_POLARITY_G => RST_POLARITY_G,
                FWFT_EN_G      => FWFT_EN_G,
                USE_DSP48_G    => USE_DSP48_G,
                XIL_DEVICE_G   => XIL_DEVICE_G,
                SYNC_STAGES_G  => SYNC_STAGES_G,
                PIPE_STAGES_G  => PIPE_STAGES_G,
                DATA_WIDTH_G   => DATA_WIDTH_G,
                ADDR_WIDTH_G   => ADDR_WIDTH_G,
                FULL_THRES_G   => FULL_THRES_G,
                EMPTY_THRES_G  => EMPTY_THRES_G)
             port map (
                rst           => rst,
                wr_clk        => wr_clk,
                wr_en         => wr_en,
                din           => din,
                wr_data_count => wr_data_count,
                wr_ack        => wr_ack,
                overflow      => overflow,
                prog_full     => prog_full,
                almost_full   => almost_full,
                full          => full,
                not_full      => not_full,
                rd_clk        => rd_clk,
                rd_en         => rd_en,
                dout          => dout,
                rd_data_count => rd_data_count,
                valid         => valid,
                underflow     => underflow,
                prog_empty    => prog_empty,
                almost_empty  => almost_empty,
                empty         => empty);
       end generate;
    end generate;

 end architecture rtl;
Fifo.SYNC_STAGES_G
SYNC_STAGES_Ginteger   range  3 to ( 2** 24):= 3
Definition: Fifo.vhd:39

FifoSyncBuiltIn.not_full
out not_fullsl
Definition: FifoSyncBuiltIn.vhd:61

Fifo.din
in dinslv(   DATA_WIDTH_G- 1 downto  0)
Definition: Fifo.vhd:52

FifoAsyncBuiltIn.wr_data_count
out wr_data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: FifoAsyncBuiltIn.vhd:53

Fifo.almost_empty
out almost_emptysl
Definition: Fifo.vhd:68

FifoAsync.rst
in rstsl
Definition: FifoAsync.vhd:45

FifoAsync.EMPTY_THRES_G
EMPTY_THRES_Ginteger   range  1 to ( 2** 24):= 1
Definition: FifoAsync.vhd:42

Fifo.wr_data_count
out wr_data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: Fifo.vhd:53

FifoSync.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger   range  4 to  48:= 4
Definition: FifoSync.vhd:40

Fifo.XIL_DEVICE_G
XIL_DEVICE_Gstring  :=   "7SERIES"
Definition: Fifo.vhd:38

Fifo.EMPTY_THRES_G
EMPTY_THRES_Ginteger   range  1 to ( 2** 24):= 1
Definition: Fifo.vhd:45

FifoSync.USE_DSP48_G
USE_DSP48_Gstring  :=   "no"
Definition: FifoSync.vhd:35

FifoAsyncBuiltIn.RST_POLARITY_G
RST_POLARITY_Gsl  := '1'
Definition: FifoAsyncBuiltIn.vhd:36

FifoAsync
Definition: FifoAsync.vhd:27

FifoAsyncBuiltIn.USE_DSP48_G
USE_DSP48_Gstring  :=   "no"
Definition: FifoAsyncBuiltIn.vhd:38

FifoSync.wr_en
in wr_ensl
Definition: FifoSync.vhd:47

FifoAsyncBuiltIn.rd_data_count
out rd_data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: FifoAsyncBuiltIn.vhd:64

FifoAsync.wr_clk
in wr_clksl
Definition: FifoAsync.vhd:47

FifoAsyncBuiltIn.almost_empty
out almost_emptysl
Definition: FifoAsyncBuiltIn.vhd:68

FifoSyncBuiltIn.prog_full
out prog_fullsl
Definition: FifoSyncBuiltIn.vhd:57

Fifo.BRAM_EN_G
BRAM_EN_Gboolean  :=   true
Definition: Fifo.vhd:32

FifoSync.prog_empty
out prog_emptysl
Definition: FifoSync.vhd:57

FifoAsyncBuiltIn.TPD_G
TPD_Gtime  :=  1 ns
Definition: FifoAsyncBuiltIn.vhd:35

FifoAsyncBuiltIn.DATA_WIDTH_G
DATA_WIDTH_Ginteger   range  1 to  72:= 18
Definition: FifoAsyncBuiltIn.vhd:42

FifoAsyncBuiltIn.dout
out doutslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoAsyncBuiltIn.vhd:63

FifoAsyncBuiltIn.almost_full
out almost_fullsl
Definition: FifoAsyncBuiltIn.vhd:57

FifoSync.rst
in rstsl  :=not    RST_POLARITY_G
Definition: FifoSync.vhd:45

FifoSyncBuiltIn.rd_en
in rd_ensl
Definition: FifoSyncBuiltIn.vhd:49

FifoAsyncBuiltIn.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger   range  9 to  13:= 10
Definition: FifoAsyncBuiltIn.vhd:43

FifoAsync.almost_full
out almost_fullsl
Definition: FifoAsync.vhd:54

StdRtlPkg.sl
std_logic   sl
Definition: StdRtlPkg.vhd:28

FifoAsync.rd_clk
in rd_clksl
Definition: FifoAsync.vhd:58

FifoAsync.RST_POLARITY_G
RST_POLARITY_Gsl  := '1'
Definition: FifoAsync.vhd:30

Fifo.FWFT_EN_G
FWFT_EN_Gboolean  :=   false
Definition: Fifo.vhd:33

FifoAsync.wr_en
in wr_ensl
Definition: FifoAsync.vhd:48

FifoAsync.PIPE_STAGES_G
PIPE_STAGES_Gnatural   range  0 to  16:= 0
Definition: FifoAsync.vhd:37

Fifo.empty
out emptysl
Definition: Fifo.vhd:69

FifoSync.BRAM_EN_G
BRAM_EN_Gboolean  :=   true
Definition: FifoSync.vhd:32

Fifo.wr_ack
out wr_acksl
Definition: Fifo.vhd:54

FifoSync.prog_full
out prog_fullsl
Definition: FifoSync.vhd:56

FifoAsyncBuiltIn.FULL_THRES_G
FULL_THRES_Ginteger   range  1 to  8190:= 1
Definition: FifoAsyncBuiltIn.vhd:44

Fifo.FULL_THRES_G
FULL_THRES_Ginteger   range  1 to ( 2** 24):= 1
Definition: Fifo.vhd:44

FifoAsync.SYNC_STAGES_G
SYNC_STAGES_Ginteger   range  3 to ( 2** 24):= 3
Definition: FifoAsync.vhd:36

FifoSync.overflow
out overflowsl
Definition: FifoSync.vhd:54

FifoSync.valid
out validsl
Definition: FifoSync.vhd:53

FifoAsync.not_full
out not_fullsl
Definition: FifoAsync.vhd:56

Fifo.RST_ASYNC_G
RST_ASYNC_Gboolean  :=   false
Definition: Fifo.vhd:30

FifoSync.data_count
out data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: FifoSync.vhd:51

Fifo.ALTERA_SYN_G
ALTERA_SYN_Gboolean  :=   false
Definition: Fifo.vhd:35

FifoAsync.rd_en
in rd_ensl
Definition: FifoAsync.vhd:59

FifoSyncBuiltIn.almost_full
out almost_fullsl
Definition: FifoSyncBuiltIn.vhd:59

Fifo.almost_full
out almost_fullsl
Definition: Fifo.vhd:57

FifoAsync.underflow
out underflowsl
Definition: FifoAsync.vhd:63

FifoSyncBuiltIn.dout
out doutslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoSyncBuiltIn.vhd:51

Fifo.rd_clk
in rd_clksl
Definition: Fifo.vhd:61

FifoSync.PIPE_STAGES_G
PIPE_STAGES_Gnatural   range  0 to  16:= 0
Definition: FifoSync.vhd:38

Fifo.USE_DSP48_G
USE_DSP48_Gstring  :=   "no"
Definition: Fifo.vhd:34

FifoSyncBuiltIn.wr_en
in wr_ensl
Definition: FifoSyncBuiltIn.vhd:48

FifoAsyncBuiltIn.valid
out validsl
Definition: FifoAsyncBuiltIn.vhd:65

Fifo.TPD_G
TPD_Gtime  :=  1 ns
Definition: Fifo.vhd:28

FifoAsync.dout
out doutslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoAsync.vhd:60

FifoSync.almost_empty
out almost_emptysl
Definition: FifoSync.vhd:59

FifoSyncBuiltIn.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger   range  9 to  13:= 10
Definition: FifoSyncBuiltIn.vhd:42

FifoSyncBuiltIn.PIPE_STAGES_G
PIPE_STAGES_Gnatural   range  0 to  16:= 0
Definition: FifoSyncBuiltIn.vhd:40

FifoSync.TPD_G
TPD_Gtime  :=  1 ns
Definition: FifoSync.vhd:29

FifoAsyncBuiltIn.EMPTY_THRES_G
EMPTY_THRES_Ginteger   range  1 to  8190:= 1
Definition: FifoAsyncBuiltIn.vhd:45

FifoSync.ALTERA_RAM_G
ALTERA_RAM_Gstring  :=   "M9K"
Definition: FifoSync.vhd:37

FifoAsync.prog_empty
out prog_emptysl
Definition: FifoAsync.vhd:64

FifoAsyncBuiltIn.XIL_DEVICE_G
XIL_DEVICE_Gstring  :=   "7SERIES"
Definition: FifoAsyncBuiltIn.vhd:39

Fifo.RST_POLARITY_G
RST_POLARITY_Gsl  := '1'
Definition: Fifo.vhd:29

FifoAsync.DATA_WIDTH_G
DATA_WIDTH_Ginteger   range  1 to ( 2** 24):= 16
Definition: FifoAsync.vhd:38

FifoAsyncBuiltIn.wr_clk
in wr_clksl
Definition: FifoAsyncBuiltIn.vhd:50

FifoAsyncBuiltIn.wr_ack
out wr_acksl
Definition: FifoAsyncBuiltIn.vhd:54

FifoSync.DATA_WIDTH_G
DATA_WIDTH_Ginteger   range  1 to ( 2** 24):= 16
Definition: FifoSync.vhd:39

FifoAsync.ALTERA_SYN_G
ALTERA_SYN_Gboolean  :=   false
Definition: FifoAsync.vhd:34

FifoAsyncBuiltIn.empty
out emptysl
Definition: FifoAsyncBuiltIn.vhd:69

Fifo.DATA_WIDTH_G
DATA_WIDTH_Ginteger   range  1 to ( 2** 24):= 16
Definition: Fifo.vhd:41

FifoSyncBuiltIn.FWFT_EN_G
FWFT_EN_Gboolean  :=   false
Definition: FifoSyncBuiltIn.vhd:37

FifoAsyncBuiltIn.FWFT_EN_G
FWFT_EN_Gboolean  :=   false
Definition: FifoAsyncBuiltIn.vhd:37

FifoAsync.INIT_G
INIT_Gslv  :=   "0"
Definition: FifoAsync.vhd:40

Fifo.wr_clk
in wr_clksl
Definition: Fifo.vhd:50

FifoAsync.ALTERA_RAM_G
ALTERA_RAM_Gstring  :=   "M9K"
Definition: FifoAsync.vhd:35

FifoAsyncBuiltIn.SYNC_STAGES_G
SYNC_STAGES_Ginteger   range  3 to ( 2** 24):= 3
Definition: FifoAsyncBuiltIn.vhd:40

FifoAsync.prog_full
out prog_fullsl
Definition: FifoAsync.vhd:53

FifoAsync.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger   range  2 to  48:= 4
Definition: FifoAsync.vhd:39

FifoAsyncBuiltIn.overflow
out overflowsl
Definition: FifoAsyncBuiltIn.vhd:55

FifoSync.din
in dinslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoSync.vhd:49

FifoSync.RST_POLARITY_G
RST_POLARITY_Gsl  := '1'
Definition: FifoSync.vhd:30

FifoSync.empty
out emptysl
Definition: FifoSync.vhd:62

FifoSyncBuiltIn.din
in dinslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoSyncBuiltIn.vhd:50

FifoSync.FULL_THRES_G
FULL_THRES_Ginteger   range  1 to ( 2** 24):= 1
Definition: FifoSync.vhd:42

FifoSyncBuiltIn.data_count
out data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: FifoSyncBuiltIn.vhd:52

FifoSyncBuiltIn.empty
out emptysl
Definition: FifoSyncBuiltIn.vhd:63

FifoSyncBuiltIn.FULL_THRES_G
FULL_THRES_Ginteger   range  1 to  8190:= 1
Definition: FifoSyncBuiltIn.vhd:43

FifoSyncBuiltIn.XIL_DEVICE_G
XIL_DEVICE_Gstring  :=   "7SERIES"
Definition: FifoSyncBuiltIn.vhd:39

FifoAsync.wr_ack
out wr_acksl
Definition: FifoAsync.vhd:51

FifoSyncBuiltIn.RST_POLARITY_G
RST_POLARITY_Gsl  := '1'
Definition: FifoSyncBuiltIn.vhd:36

FifoAsync.empty
out emptysl
Definition: FifoAsync.vhd:66

FifoSyncBuiltIn.rst
in rstsl  := '0'
Definition: FifoSyncBuiltIn.vhd:46

Fifo.full
out fullsl
Definition: Fifo.vhd:58

Fifo.valid
out validsl
Definition: Fifo.vhd:65

FifoSyncBuiltIn.EMPTY_THRES_G
EMPTY_THRES_Ginteger   range  1 to  8190:= 1
Definition: FifoSyncBuiltIn.vhd:44

FifoAsyncBuiltIn.prog_empty
out prog_emptysl
Definition: FifoAsyncBuiltIn.vhd:67

Fifo.rd_en
in rd_ensl  := '0'
Definition: Fifo.vhd:62

Fifo.underflow
out underflowsl
Definition: Fifo.vhd:66

FifoSyncBuiltIn.DATA_WIDTH_G
DATA_WIDTH_Ginteger   range  1 to  72:= 18
Definition: FifoSyncBuiltIn.vhd:41

FifoSync.underflow
out underflowsl
Definition: FifoSync.vhd:55

FifoAsyncBuiltIn.full
out fullsl
Definition: FifoAsyncBuiltIn.vhd:58

Fifo.overflow
out overflowsl
Definition: Fifo.vhd:55

Fifo.ALTERA_RAM_G
ALTERA_RAM_Gstring  :=   "M9K"
Definition: Fifo.vhd:36

FifoAsyncBuiltIn.rd_en
in rd_ensl
Definition: FifoAsyncBuiltIn.vhd:62

FifoAsyncBuiltIn.din
in dinslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoAsyncBuiltIn.vhd:52

FifoAsyncBuiltIn.underflow
out underflowsl
Definition: FifoAsyncBuiltIn.vhd:66

FifoSync.dout
out doutslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoSync.vhd:50

FifoSync
Definition: FifoSync.vhd:27

FifoAsync.rd_data_count
out rd_data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: FifoAsync.vhd:61

FifoAsync.USE_DSP48_G
USE_DSP48_Gstring  :=   "no"
Definition: FifoAsync.vhd:33

Fifo.GEN_SYNC_FIFO_G
GEN_SYNC_FIFO_Gboolean  :=   false
Definition: Fifo.vhd:31

FifoSync.clk
in clksl
Definition: FifoSync.vhd:46

FifoAsync.overflow
out overflowsl
Definition: FifoAsync.vhd:52

FifoSyncBuiltIn
Definition: FifoSyncBuiltIn.vhd:33

FifoSync.rd_en
in rd_ensl
Definition: FifoSync.vhd:48

Fifo.INIT_G
INIT_Gslv  :=   "0"
Definition: Fifo.vhd:43

Fifo.not_full
out not_fullsl
Definition: Fifo.vhd:59

FifoSyncBuiltIn.wr_ack
out wr_acksl
Definition: FifoSyncBuiltIn.vhd:53

FifoAsync.FWFT_EN_G
FWFT_EN_Gboolean  :=   false
Definition: FifoAsync.vhd:32

Fifo.dout
out doutslv(   DATA_WIDTH_G- 1 downto  0)
Definition: Fifo.vhd:63

Fifo.rst
in rstsl  :=not    RST_POLARITY_G
Definition: Fifo.vhd:48

FifoSync.almost_full
out almost_fullsl
Definition: FifoSync.vhd:58

FifoSync.RST_ASYNC_G
RST_ASYNC_Gboolean  :=   false
Definition: FifoSync.vhd:31

FifoSyncBuiltIn.valid
out validsl
Definition: FifoSyncBuiltIn.vhd:54

Fifo.PIPE_STAGES_G
PIPE_STAGES_Gnatural   range  0 to  16:= 0
Definition: Fifo.vhd:40

FifoAsyncBuiltIn.not_full
out not_fullsl
Definition: FifoAsyncBuiltIn.vhd:59

FifoAsyncBuiltIn.rd_clk
in rd_clksl
Definition: FifoAsyncBuiltIn.vhd:61

FifoSyncBuiltIn.overflow
out overflowsl
Definition: FifoSyncBuiltIn.vhd:55

FifoSyncBuiltIn.prog_empty
out prog_emptysl
Definition: FifoSyncBuiltIn.vhd:58

Fifo.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger   range  4 to  48:= 4
Definition: Fifo.vhd:42

FifoSync.FWFT_EN_G
FWFT_EN_Gboolean  :=   false
Definition: FifoSync.vhd:34

FifoAsync.FULL_THRES_G
FULL_THRES_Ginteger   range  1 to ( 2** 24):= 1
Definition: FifoAsync.vhd:41

FifoSync.wr_ack
out wr_acksl
Definition: FifoSync.vhd:52

FifoAsync.din
in dinslv(   DATA_WIDTH_G- 1 downto  0)
Definition: FifoAsync.vhd:49

Fifo.USE_BUILT_IN_G
USE_BUILT_IN_Gboolean  :=   false
Definition: Fifo.vhd:37

FifoAsync.full
out fullsl
Definition: FifoAsync.vhd:55

FifoSyncBuiltIn.full
out fullsl
Definition: FifoSyncBuiltIn.vhd:62

FifoAsync.wr_data_count
out wr_data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: FifoAsync.vhd:50

FifoSync.not_full
out not_fullsl
Definition: FifoSync.vhd:61

FifoAsyncBuiltIn.wr_en
in wr_ensl
Definition: FifoAsyncBuiltIn.vhd:51

FifoAsyncBuiltIn.prog_full
out prog_fullsl
Definition: FifoAsyncBuiltIn.vhd:56

StdRtlPkg
Definition: StdRtlPkg.vhd:23

FifoSyncBuiltIn.underflow
out underflowsl
Definition: FifoSyncBuiltIn.vhd:56

FifoAsyncBuiltIn
Definition: FifoAsyncBuiltIn.vhd:33

FifoAsync.valid
out validsl
Definition: FifoAsync.vhd:62

FifoSyncBuiltIn.TPD_G
TPD_Gtime  :=  1 ns
Definition: FifoSyncBuiltIn.vhd:35

Fifo.prog_full
out prog_fullsl
Definition: Fifo.vhd:56

FifoSync.INIT_G
INIT_Gslv  :=   "0"
Definition: FifoSync.vhd:41

FifoSync.EMPTY_THRES_G
EMPTY_THRES_Ginteger   range  1 to ( 2** 24):= 1
Definition: FifoSync.vhd:43

FifoSync.full
out fullsl
Definition: FifoSync.vhd:60

Fifo.rd_data_count
out rd_data_countslv(   ADDR_WIDTH_G- 1 downto  0)
Definition: Fifo.vhd:64

FifoSyncBuiltIn.almost_empty
out almost_emptysl
Definition: FifoSyncBuiltIn.vhd:60

Fifo.prog_empty
out prog_emptysl
Definition: Fifo.vhd:67

FifoSyncBuiltIn.USE_DSP48_G
USE_DSP48_Gstring  :=   "no"
Definition: FifoSyncBuiltIn.vhd:38

FifoAsync.BRAM_EN_G
BRAM_EN_Gboolean  :=   true
Definition: FifoAsync.vhd:31

FifoSyncBuiltIn.clk
in clksl
Definition: FifoSyncBuiltIn.vhd:47

FifoAsyncBuiltIn.PIPE_STAGES_G
PIPE_STAGES_Gnatural   range  0 to  16:= 0
Definition: FifoAsyncBuiltIn.vhd:41

SlvArraytoAxiLite.ieee
_library_ ieeeieee
Definition: SlvArraytoAxiLite.vhd:18

Fifo
Definition: Fifo.vhd:26

FifoAsyncBuiltIn.rst
in rstsl
Definition: FifoAsyncBuiltIn.vhd:48

StdRtlPkg.slv
std_logic_vector   slv
Definition: StdRtlPkg.vhd:29

FifoAsync.TPD_G
TPD_Gtime  :=  1 ns
Definition: FifoAsync.vhd:29

FifoAsync.almost_empty
out almost_emptysl
Definition: FifoAsync.vhd:65

Fifo.wr_en
in wr_ensl  := '0'
Definition: Fifo.vhd:51