SURF  1.0
Generics | Ports | Libraries | Use Clauses
SlvArraytoAxiLite Entity Reference
axi
+ Inheritance diagram for SlvArraytoAxiLite:
+ Collaboration diagram for SlvArraytoAxiLite:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiLiteMasterPkg  Package <AxiLiteMasterPkg>

Generics

TPD_G  time := 1 ns
COMMON_CLK_G  boolean := false
SIZE_G  positive := 1
ADDR_G  Slv32Array := ( 0 = > x " 00000000 " )

Ports

clk   in sl
rst   in sl
input   in Slv32Array ( SIZE_G - 1 downto 0 )
axilClk   in sl
axilRst   in sl
axilReadMaster   out AxiLiteReadMasterType
axilReadSlave   in AxiLiteReadSlaveType
axilWriteMaster   out AxiLiteWriteMasterType
axilWriteSlave   in AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 29 of file SlvArraytoAxiLite.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file SlvArraytoAxiLite.vhd.

◆ COMMON_CLK_G

COMMON_CLK_G boolean := false
Generic

Definition at line 32 of file SlvArraytoAxiLite.vhd.

◆ SIZE_G

SIZE_G positive := 1
Generic

Definition at line 33 of file SlvArraytoAxiLite.vhd.

◆ ADDR_G

ADDR_G Slv32Array := ( 0 = > x " 00000000 " )
Generic

Definition at line 34 of file SlvArraytoAxiLite.vhd.

◆ clk

clk in sl
Port

Definition at line 37 of file SlvArraytoAxiLite.vhd.

◆ rst

rst in sl
Port

Definition at line 38 of file SlvArraytoAxiLite.vhd.

◆ input

input in Slv32Array ( SIZE_G - 1 downto 0 )
Port

Definition at line 39 of file SlvArraytoAxiLite.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 41 of file SlvArraytoAxiLite.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 42 of file SlvArraytoAxiLite.vhd.

◆ axilReadMaster

axilReadMaster out AxiLiteReadMasterType
Port

Definition at line 43 of file SlvArraytoAxiLite.vhd.

◆ axilReadSlave

axilReadSlave in AxiLiteReadSlaveType
Port

Definition at line 44 of file SlvArraytoAxiLite.vhd.

◆ axilWriteMaster

axilWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 45 of file SlvArraytoAxiLite.vhd.

◆ axilWriteSlave

axilWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 46 of file SlvArraytoAxiLite.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file SlvArraytoAxiLite.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file SlvArraytoAxiLite.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file SlvArraytoAxiLite.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file SlvArraytoAxiLite.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file SlvArraytoAxiLite.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file SlvArraytoAxiLite.vhd.

◆ AxiLiteMasterPkg

AxiLiteMasterPkg
Package

Definition at line 25 of file SlvArraytoAxiLite.vhd.

The documentation for this class was generated from the following file: