SURF  1.0
Generics | Ports | Libraries | Use Clauses
FifoSync Entity Reference
base » fifo
+ Inheritance diagram for FifoSync:
+ Collaboration diagram for FifoSync:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
RST_POLARITY_G  sl := ' 1 '
RST_ASYNC_G  boolean := false
BRAM_EN_G  boolean := true
BYP_RAM_G  boolean := false
FWFT_EN_G  boolean := false
USE_DSP48_G  string := " no "
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
PIPE_STAGES_G  natural range 0 to 16 := 0
DATA_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 16
ADDR_WIDTH_G  integer range 4 to 48 := 4
INIT_G  slv := " 0 "
FULL_THRES_G  integer range 1 to ( 2 ** 24 ) := 1
EMPTY_THRES_G  integer range 1 to ( 2 ** 24 ) := 1

Ports

rst   in sl := not RST_POLARITY_G
clk   in sl
wr_en   in sl
rd_en   in sl
din   in slv ( DATA_WIDTH_G - 1 downto 0 )
dout   out slv ( DATA_WIDTH_G - 1 downto 0 )
data_count   out slv ( ADDR_WIDTH_G - 1 downto 0 )
wr_ack   out sl
valid   out sl
overflow   out sl
underflow   out sl
prog_full   out sl
prog_empty   out sl
almost_full   out sl
almost_empty   out sl
full   out sl
not_full   out sl
empty   out sl

Detailed Description

See also
entity

Definition at line 27 of file FifoSync.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file FifoSync.vhd.

◆ RST_POLARITY_G

RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 30 of file FifoSync.vhd.

◆ RST_ASYNC_G

RST_ASYNC_G boolean := false
Generic

Definition at line 31 of file FifoSync.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 32 of file FifoSync.vhd.

◆ BYP_RAM_G

BYP_RAM_G boolean := false
Generic

Definition at line 33 of file FifoSync.vhd.

◆ FWFT_EN_G

FWFT_EN_G boolean := false
Generic

Definition at line 34 of file FifoSync.vhd.

◆ USE_DSP48_G

USE_DSP48_G string := " no "
Generic

Definition at line 35 of file FifoSync.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 36 of file FifoSync.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 37 of file FifoSync.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 38 of file FifoSync.vhd.

◆ DATA_WIDTH_G

DATA_WIDTH_G integer range 1 to ( 2 ** 24 ) := 16
Generic

Definition at line 39 of file FifoSync.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G integer range 4 to 48 := 4
Generic

Definition at line 40 of file FifoSync.vhd.

◆ INIT_G

INIT_G slv := " 0 "
Generic

Definition at line 41 of file FifoSync.vhd.

◆ FULL_THRES_G

FULL_THRES_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 42 of file FifoSync.vhd.

◆ EMPTY_THRES_G

EMPTY_THRES_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 43 of file FifoSync.vhd.

◆ rst

rst in sl := not RST_POLARITY_G
Port

Definition at line 45 of file FifoSync.vhd.

◆ clk

clk in sl
Port

Definition at line 46 of file FifoSync.vhd.

◆ wr_en

wr_en in sl
Port

Definition at line 47 of file FifoSync.vhd.

◆ rd_en

rd_en in sl
Port

Definition at line 48 of file FifoSync.vhd.

◆ din

din in slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 49 of file FifoSync.vhd.

◆ dout

dout out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 50 of file FifoSync.vhd.

◆ data_count

data_count out slv ( ADDR_WIDTH_G - 1 downto 0 )
Port

Definition at line 51 of file FifoSync.vhd.

◆ wr_ack

wr_ack out sl
Port

Definition at line 52 of file FifoSync.vhd.

◆ valid

valid out sl
Port

Definition at line 53 of file FifoSync.vhd.

◆ overflow

overflow out sl
Port

Definition at line 54 of file FifoSync.vhd.

◆ underflow

underflow out sl
Port

Definition at line 55 of file FifoSync.vhd.

◆ prog_full

prog_full out sl
Port

Definition at line 56 of file FifoSync.vhd.

◆ prog_empty

prog_empty out sl
Port

Definition at line 57 of file FifoSync.vhd.

◆ almost_full

almost_full out sl
Port

Definition at line 58 of file FifoSync.vhd.

◆ almost_empty

almost_empty out sl
Port

Definition at line 59 of file FifoSync.vhd.

◆ full

full out sl
Port

Definition at line 60 of file FifoSync.vhd.

◆ not_full

not_full out sl
Port

Definition at line 61 of file FifoSync.vhd.

◆ empty

empty out sl
Port

Definition at line 62 of file FifoSync.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file FifoSync.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file FifoSync.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file FifoSync.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file FifoSync.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file FifoSync.vhd.

The documentation for this class was generated from the following file: