SURF  1.0
Generics | Ports | Libraries | Use Clauses
UartBrg Entity Reference
protocols » uart
+ Inheritance diagram for UartBrg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>

Generics

CLK_FREQ_G  real := 125 . 0E6
BAUD_RATE_G  integer := 115200
MULTIPLIER_G  integer := 16

Ports

clk   in sl
rst   in sl
clkEn   out sl

Detailed Description

See also
entity

Definition at line 25 of file UartBrg.vhd.

Member Data Documentation

◆ CLK_FREQ_G

CLK_FREQ_G real := 125 . 0E6
Generic

Definition at line 28 of file UartBrg.vhd.

◆ BAUD_RATE_G

BAUD_RATE_G integer := 115200
Generic

Definition at line 29 of file UartBrg.vhd.

◆ MULTIPLIER_G

MULTIPLIER_G integer := 16
Generic

Definition at line 30 of file UartBrg.vhd.

◆ clk

clk in sl
Port

Definition at line 32 of file UartBrg.vhd.

◆ rst

rst in sl
Port

Definition at line 33 of file UartBrg.vhd.

◆ clkEn

clkEn out sl
Port

Definition at line 34 of file UartBrg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file UartBrg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file UartBrg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file UartBrg.vhd.

The documentation for this class was generated from the following file: