SURF  1.0
Generics | Ports | Libraries | Use Clauses
UartTx Entity Reference
protocols » uart
+ Inheritance diagram for UartTx:

Entities

RTL  architecture
 

Libraries

IEEE 

Use Clauses

std_logic_1164 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns

Ports

clk   in sl
rst   in sl
baud16x   in sl
wrData   in slv ( 7 downto 0 )
wrValid   in sl
wrReady   out sl
tx   out sl

Detailed Description

See also
entity

Definition at line 26 of file UartTx.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 28 of file UartTx.vhd.

◆ clk

clk in sl
Port

Definition at line 30 of file UartTx.vhd.

◆ rst

rst in sl
Port

Definition at line 31 of file UartTx.vhd.

◆ baud16x

baud16x in sl
Port

Definition at line 32 of file UartTx.vhd.

◆ wrData

wrData in slv ( 7 downto 0 )
Port

Definition at line 33 of file UartTx.vhd.

◆ wrValid

wrValid in sl
Port

Definition at line 34 of file UartTx.vhd.

◆ wrReady

wrReady out sl
Port

Definition at line 35 of file UartTx.vhd.

◆ tx

tx out sl
Port

Definition at line 36 of file UartTx.vhd.

◆ IEEE

IEEE
Library

Definition at line 18 of file UartTx.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file UartTx.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file UartTx.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file UartTx.vhd.

The documentation for this class was generated from the following file: