1 ------------------------------------------------------------------------------- 2 -- File : Pgp2bGtp7VarLatWrapper.vhd 3 -- Company : SLAC National Accelerator Laboratory 4 -- Created : 2014-01-29 5 -- Last update: 2016-12-16 6 ------------------------------------------------------------------------------- 7 -- Description: Example PGP2b front end wrapper 8 -- Note: Default generic configurations are for the AC701 development board 9 -- Note: Default uses 125 MHz reference clock to generate 3.125 Gbps PGP link 10 ------------------------------------------------------------------------------- 11 -- This file is part of 'SLAC Firmware Standard Library'. 12 -- It is subject to the license terms in the LICENSE.txt file found in the 13 -- top-level directory of this distribution and at: 14 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 15 -- No part of 'SLAC Firmware Standard Library', including this file, 16 -- may be copied, modified, propagated, or distributed except according to 17 -- the terms contained in the LICENSE.txt file. 18 ------------------------------------------------------------------------------- 21 use ieee.std_logic_1164.
all;
29 use unisim.vcomponents.
all;
32 --! @ingroup protocols_pgp_pgp2b_gtp7 37 -- MMCM Configurations 42 -- Quad PLL Configurations (Defaults: gtClkP = 125 MHz Configuration) 47 -- MGT Configurations (Defaults: gtClkP = 125 MHz Configuration) 100 end Pgp2bGtp7VarLatWrapper;
129 IBUFDS_GTE2_Inst : IBUFDS_GTE2
142 RstSync_Inst :
entity work.
RstSync 211 -- MGT Configurations 220 -- Configure PLL sources 261 -- Frame TX Interface 264 -- Frame RX Interface 271 -- AXI-Lite Interface out qPllRefClkLostslv( 1 downto 0)
in qPllRefClkslv( 1 downto 0)
RX_CLK25_DIV_Gnatural := 5
QPLL_FBDIV_IN_Gnatural range 1 to 5:= 5
array(natural range <> ) of AxiStreamSlaveType AxiStreamSlaveArray
TX_CLK25_DIV_Gnatural := 5
PAYLOAD_CNT_TOP_Ginteger := 7
slv( 1 downto 0) gtQPllRefClkLost
PLL0_FBDIV_45_IN_Ginteger range 4 to 5:= 5
RX_ENABLE_Gboolean := true
CLKIN_PERIOD_Greal := 6.4
slv( 1 downto 0) pllRefClk
SIM_GTRESET_SPEEDUP_Gstring := "FALSE"
RXLPM_INCM_CFG_Gbit := '0'
slv( 1 downto 0) gtQPllOutClk
CLKOUT0_DIVIDE_F_Greal range 1.0 to 128.0:= 6.0
TX_ENABLE_Gboolean := true
in txPreCursorslv( 4 downto 0) :=( others => '0')
out qPllOutClkslv( 1 downto 0)
RX_CLK25_DIV_Ginteger := 7
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
RXCDR_CFG_Gbit_vector := x"0001107FE206021081010"
out axilWriteSlaveAxiLiteWriteSlaveType
in pgpRxCtrlAxiStreamCtrlArray( 3 downto 0)
RX_OS_CFG_Gbit_vector := "0000010000000"
CLKIN_PERIOD_Greal := 10.0
PLL0_REFCLK_SEL_Gbit_vector := "001"
RXCDR_CFG_Gbit_vector := x"0000107FE206001041010"
slv( 1 downto 0) gtQPllReset
out pgpTxSlavesAxiStreamSlaveArray( 3 downto 0)
RST_IN_POLARITY_Gsl := '1'
slv( 1 downto 0) gtQPllLock
PLL0_FBDIV_IN_Ginteger range 1 to 5:= 4
in gtQPllOutRefClkslv( 1 downto 0)
out axilReadSlaveAxiLiteReadSlaveType
PLL0_REFCLK_DIV_IN_Ginteger range 1 to 2:= 1
QPLL_REFCLK_DIV_IN_Gnatural range 1 to 2:= 1
RX_OS_CFG_Gbit_vector := "0001111110000"
out pgpTxOutPgp2bTxOutType
PLL1_REFCLK_SEL_Gbit_vector := "001"
in gtQPllOutClkslv( 1 downto 0)
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
INPUT_BUFG_Gboolean := true
in gtQPllLockslv( 1 downto 0)
PAYLOAD_CNT_TOP_Ginteger := 7
SIMULATION_Gboolean := false
out pgpRxOutPgp2bRxOutType
QPLL_REFCLK_SEL_Gbit_vector := "001"
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
DIVCLK_DIVIDE_Gnatural range 1 to 106:= 1
in gtQPllRefClkLostslv( 1 downto 0)
VC_INTERLEAVE_Ginteger := 0
in txDiffCtrlslv( 3 downto 0) := "1000"
in txPreCursorslv( 4 downto 0) :=( others => '0')
TX_ENABLE_Gboolean := true
NUM_VC_EN_Ginteger range 1 to 4:= 4
in txPostCursorslv( 4 downto 0) :=( others => '0')
PLL1_REFCLK_DIV_IN_Ginteger range 1 to 2:= 1
slv( 1 downto 0) := "11" AXI_RESP_DECERR_C
TX_CLK25_DIV_Ginteger := 7
out pgpTxOutPgp2bTxOutType
slv( 1 downto 0) qPllReset
slv( 1 downto 0) pllLockDetClk
SIM_RESET_SPEEDUP_Gstring := "TRUE"
BANDWIDTH_Gstring := "OPTIMIZED"
out axilReadSlaveAxiLiteReadSlaveType
in txDiffCtrlslv( 3 downto 0) := "1000"
in pgpRxMmcmLockedsl := '1'
RXLPM_INCM_CFG_Gbit := '1'
CLKFBOUT_MULT_F_Greal range 1.0 to 64.0:= 1.0
in txPostCursorslv( 4 downto 0) :=( others => '0')
DIVCLK_DIVIDE_Ginteger range 1 to 106:= 1
out gtQPllResetslv( 1 downto 0)
out pgpRxOutPgp2bRxOutType
in pgpRxCtrlAxiStreamCtrlArray( 3 downto 0)
in pgpTxMastersAxiStreamMasterArray( 3 downto 0) :=( others => AXI_STREAM_MASTER_INIT_C)
array(natural range <> ) of AxiStreamCtrlType AxiStreamCtrlArray
RXLPM_IPCM_CFG_Gbit := '1'
out pgpRxMastersAxiStreamMasterArray( 3 downto 0)
RX_ENABLE_Gboolean := true
array(natural range <> ) of AxiStreamMasterType AxiStreamMasterArray
CLKFBOUT_MULT_F_Greal range 1.0 to 64.0:= 6.0
AxiLiteReadMasterType :=(araddr =>( others => '0'),arprot =>( others => '0'),arvalid => '0',rready => '1') AXI_LITE_READ_MASTER_INIT_C
in qPllResetslv( 1 downto 0)
CLKOUT0_DIVIDE_F_Greal range 1.0 to 128.0:= 1.0
in qPllLockDetClkslv( 1 downto 0)
NUM_VC_EN_Ginteger range 1 to 4:= 4
AxiLiteWriteMasterType :=(awaddr =>( others => '0'),awprot =>( others => '0'),awvalid => '0',wdata =>( others => '0'),wstrb =>( others => '1'),wvalid => '0',bready => '1') AXI_LITE_WRITE_MASTER_INIT_C
in pgpTxMmcmLockedsl := '1'
out pgpTxSlavesAxiStreamSlaveArray( 3 downto 0)
out pgpRxMastersAxiStreamMasterArray( 3 downto 0)
QPLL_FBDIV_45_IN_Gnatural range 4 to 5:= 5
out axilWriteSlaveAxiLiteWriteSlaveType
out qPllOutRefClkslv( 1 downto 0)
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
PLL1_FBDIV_45_IN_Ginteger range 4 to 5:= 5
RXLPM_IPCM_CFG_Gbit := '0'
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
out qPllLockslv( 1 downto 0)
VC_INTERLEAVE_Ginteger := 1
slv( 1 downto 0) gtQPllOutRefClk
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
NUM_CLOCKS_Ginteger range 1 to 7
PLL1_FBDIV_IN_Ginteger range 1 to 5:= 4
in pgpTxMastersAxiStreamMasterArray( 3 downto 0)
1.8.13