SURF  1.0
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Gtp7QuadPll Entity Reference
xilinx » 7Series » gtp7
+ Inheritance diagram for Gtp7QuadPll:
+ Collaboration diagram for Gtp7QuadPll:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
numeric_std 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
vcomponents 

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
SIM_RESET_SPEEDUP_G  string := " TRUE "
SIM_VERSION_G  string := " 1.0 "
PLL0_REFCLK_SEL_G  bit_vector := " 001 "
PLL0_FBDIV_IN_G  integer range 1 to 5 := 4
PLL0_FBDIV_45_IN_G  integer range 4 to 5 := 5
PLL0_REFCLK_DIV_IN_G  integer range 1 to 2 := 1
PLL1_REFCLK_SEL_G  bit_vector := " 001 "
PLL1_FBDIV_IN_G  integer range 1 to 5 := 4
PLL1_FBDIV_45_IN_G  integer range 4 to 5 := 5
PLL1_REFCLK_DIV_IN_G  integer range 1 to 2 := 1

Ports

qPllRefClk   in slv ( 1 downto 0 )
qPllOutClk   out slv ( 1 downto 0 )
qPllOutRefClk   out slv ( 1 downto 0 )
qPllLock   out slv ( 1 downto 0 )
qPllLockDetClk   in slv ( 1 downto 0 )
qPllRefClkLost   out slv ( 1 downto 0 )
qPllPowerDown   in slv ( 1 downto 0 ) := ( others = > ' 0 ' )
qPllReset   in slv ( 1 downto 0 )
axilClk   in sl := ' 0 '
axilRst   in sl := ' 0 '
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 30 of file Gtp7QuadPll.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file Gtp7QuadPll.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 33 of file Gtp7QuadPll.vhd.

◆ SIM_RESET_SPEEDUP_G

SIM_RESET_SPEEDUP_G string := " TRUE "
Generic

Definition at line 34 of file Gtp7QuadPll.vhd.

◆ SIM_VERSION_G

SIM_VERSION_G string := " 1.0 "
Generic

Definition at line 35 of file Gtp7QuadPll.vhd.

◆ PLL0_REFCLK_SEL_G

PLL0_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 36 of file Gtp7QuadPll.vhd.

◆ PLL0_FBDIV_IN_G

PLL0_FBDIV_IN_G integer range 1 to 5 := 4
Generic

Definition at line 37 of file Gtp7QuadPll.vhd.

◆ PLL0_FBDIV_45_IN_G

PLL0_FBDIV_45_IN_G integer range 4 to 5 := 5
Generic

Definition at line 38 of file Gtp7QuadPll.vhd.

◆ PLL0_REFCLK_DIV_IN_G

PLL0_REFCLK_DIV_IN_G integer range 1 to 2 := 1
Generic

Definition at line 39 of file Gtp7QuadPll.vhd.

◆ PLL1_REFCLK_SEL_G

PLL1_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 40 of file Gtp7QuadPll.vhd.

◆ PLL1_FBDIV_IN_G

PLL1_FBDIV_IN_G integer range 1 to 5 := 4
Generic

Definition at line 41 of file Gtp7QuadPll.vhd.

◆ PLL1_FBDIV_45_IN_G

PLL1_FBDIV_45_IN_G integer range 4 to 5 := 5
Generic

Definition at line 42 of file Gtp7QuadPll.vhd.

◆ PLL1_REFCLK_DIV_IN_G

PLL1_REFCLK_DIV_IN_G integer range 1 to 2 := 1
Generic

Definition at line 43 of file Gtp7QuadPll.vhd.

◆ qPllRefClk

qPllRefClk in slv ( 1 downto 0 )
Port

Definition at line 45 of file Gtp7QuadPll.vhd.

◆ qPllOutClk

qPllOutClk out slv ( 1 downto 0 )
Port

Definition at line 46 of file Gtp7QuadPll.vhd.

◆ qPllOutRefClk

qPllOutRefClk out slv ( 1 downto 0 )
Port

Definition at line 47 of file Gtp7QuadPll.vhd.

◆ qPllLock

qPllLock out slv ( 1 downto 0 )
Port

Definition at line 48 of file Gtp7QuadPll.vhd.

◆ qPllLockDetClk

qPllLockDetClk in slv ( 1 downto 0 )
Port

Definition at line 49 of file Gtp7QuadPll.vhd.

◆ qPllRefClkLost

qPllRefClkLost out slv ( 1 downto 0 )
Port

Definition at line 50 of file Gtp7QuadPll.vhd.

◆ qPllPowerDown

qPllPowerDown in slv ( 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 51 of file Gtp7QuadPll.vhd.

◆ qPllReset

qPllReset in slv ( 1 downto 0 )
Port

Definition at line 52 of file Gtp7QuadPll.vhd.

◆ axilClk

axilClk in sl := ' 0 '
Port

Definition at line 54 of file Gtp7QuadPll.vhd.

◆ axilRst

axilRst in sl := ' 0 '
Port

Definition at line 55 of file Gtp7QuadPll.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 56 of file Gtp7QuadPll.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 57 of file Gtp7QuadPll.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 58 of file Gtp7QuadPll.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 59 of file Gtp7QuadPll.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file Gtp7QuadPll.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file Gtp7QuadPll.vhd.

◆ numeric_std

numeric_std
Package

Definition at line 20 of file Gtp7QuadPll.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file Gtp7QuadPll.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 23 of file Gtp7QuadPll.vhd.

◆ unisim

unisim
Library

Definition at line 25 of file Gtp7QuadPll.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 26 of file Gtp7QuadPll.vhd.

The documentation for this class was generated from the following file: