SURF  1.0
Gtp7QuadPll.vhd
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1 -------------------------------------------------------------------------------
2 -- File : Gtp7QuadPll.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2013-06-29
5 -- Last update: 2016-03-08
6 -------------------------------------------------------------------------------
7 -- Description: Wrapper for Xilinx 7-series GTP's QPLL
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.numeric_std.all;
21 
22 use work.StdRtlPkg.all;
23 use work.AxiLitePkg.all;
24 
25 library unisim;
26 use unisim.vcomponents.all;
27 
28 --! @see entity
29  --! @ingroup xilinx_7Series_gtp7
30 entity Gtp7QuadPll is
31  generic (
32  TPD_G : time := 1 ns;
33  AXI_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_DECERR_C;
34  SIM_RESET_SPEEDUP_G : string := "TRUE";
35  SIM_VERSION_G : string := "1.0";
36  PLL0_REFCLK_SEL_G : bit_vector := "001";
37  PLL0_FBDIV_IN_G : integer range 1 to 5 := 4;
38  PLL0_FBDIV_45_IN_G : integer range 4 to 5 := 5;
39  PLL0_REFCLK_DIV_IN_G : integer range 1 to 2 := 1;
40  PLL1_REFCLK_SEL_G : bit_vector := "001";
41  PLL1_FBDIV_IN_G : integer range 1 to 5 := 4;
42  PLL1_FBDIV_45_IN_G : integer range 4 to 5 := 5;
43  PLL1_REFCLK_DIV_IN_G : integer range 1 to 2 := 1);
44  port (
45  qPllRefClk : in slv(1 downto 0);
46  qPllOutClk : out slv(1 downto 0);
47  qPllOutRefClk : out slv(1 downto 0);
48  qPllLock : out slv(1 downto 0);
49  qPllLockDetClk : in slv(1 downto 0); -- Lock detect clock
50  qPllRefClkLost : out slv(1 downto 0);
51  qPllPowerDown : in slv(1 downto 0) := (others => '0');
52  qPllReset : in slv(1 downto 0);
53  -- AXI-Lite Interface
54  axilClk : in sl := '0';
55  axilRst : in sl := '0';
56  axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
57  axilReadSlave : out AxiLiteReadSlaveType;
58  axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
59  axilWriteSlave : out AxiLiteWriteSlaveType);
60 end entity Gtp7QuadPll;
61 
62 architecture mapping of Gtp7QuadPll is
63 
64  signal gtRefClk0 : sl;
65  signal gtRefClk1 : sl;
66  signal gtEastRefClk0 : sl;
67  signal gtEastRefClk1 : sl;
68  signal gtWestRefClk0 : sl;
69  signal gtWestRefClk1 : sl;
70  signal gtGRefClk0 : sl;
71  signal gtGRefClk1 : sl;
72 
73  signal drpEn : sl;
74  signal drpWe : sl;
75  signal drpRdy : sl;
76  signal drpAddr : slv(7 downto 0);
77  signal drpDi : slv(15 downto 0);
78  signal drpDo : slv(15 downto 0);
79 
80 begin
81 
82  --------------------------------------------------------------------------------------------------
83  -- QPLL clock select. Only ever use 1 clock to drive qpll. Never switch clocks.
84  --------------------------------------------------------------------------------------------------
85  gtRefClk0 <= qpllRefClk(0) when (PLL0_REFCLK_SEL_G = "001") else qpllRefClk(1) when (PLL1_REFCLK_SEL_G = "001") else '0';
86  gtRefClk1 <= qpllRefClk(0) when (PLL0_REFCLK_SEL_G = "010") else qpllRefClk(1) when (PLL1_REFCLK_SEL_G = "010") else '0';
87  gtEastRefClk0 <= qpllRefClk(0) when (PLL0_REFCLK_SEL_G = "011") else qpllRefClk(1) when (PLL1_REFCLK_SEL_G = "011") else '0';
88  gtEastRefClk1 <= qpllRefClk(0) when (PLL0_REFCLK_SEL_G = "100") else qpllRefClk(1) when (PLL1_REFCLK_SEL_G = "100") else '0';
89  gtWestRefClk0 <= qpllRefClk(0) when (PLL0_REFCLK_SEL_G = "101") else qpllRefClk(1) when (PLL1_REFCLK_SEL_G = "101") else '0';
90  gtWestRefClk1 <= qpllRefClk(0) when (PLL0_REFCLK_SEL_G = "110") else qpllRefClk(1) when (PLL1_REFCLK_SEL_G = "110") else '0';
91  gtGRefClk0 <= qpllRefClk(0) when (PLL0_REFCLK_SEL_G = "111") else '0';
92  gtGRefClk1 <= qpllRefClk(1) when (PLL1_REFCLK_SEL_G = "111") else '0';
93 
94  gtpe2_common_0_i : GTPE2_COMMON
95  generic map(
96  -- Simulation attributes
97  SIM_RESET_SPEEDUP => SIM_RESET_SPEEDUP_G,
98  SIM_PLL0REFCLK_SEL => PLL0_REFCLK_SEL_G,
99  SIM_PLL1REFCLK_SEL => PLL1_REFCLK_SEL_G,
100  SIM_VERSION => SIM_VERSION_G,
101  -- COMMON BLOCK Attributes
102  BIAS_CFG => (x"0000000000050001"),
103  COMMON_CFG => (x"00000000"),
104  RSVD_ATTR0 => (x"0000"),
105  RSVD_ATTR1 => (x"0000"),
106  -- PLL0 Attributes
107  PLL0_FBDIV => PLL0_FBDIV_IN_G,
108  PLL0_FBDIV_45 => PLL0_FBDIV_45_IN_G,
109  PLL0_REFCLK_DIV => PLL0_REFCLK_DIV_IN_G,
110  PLL0_CFG => (x"01F03DC"),
111  PLL0_DMON_CFG => ('0'),
112  PLL0_INIT_CFG => (x"00001E"),
113  PLL0_LOCK_CFG => (x"1E8"),
114  -- PLL1 Attributes
115  PLL1_FBDIV => PLL1_FBDIV_IN_G,
116  PLL1_FBDIV_45 => PLL1_FBDIV_45_IN_G,
117  PLL1_REFCLK_DIV => PLL1_REFCLK_DIV_IN_G,
118  PLL1_CFG => (x"01F03DC"),
119  PLL1_DMON_CFG => ('0'),
120  PLL1_INIT_CFG => (x"00001E"),
121  PLL1_LOCK_CFG => (x"1E8"),
122  PLL_CLKOUT_CFG => (x"00"))
123  port map(
124  -- Dynamic Reconfiguration Port (DRP)
125  DRPADDR => drpAddr,
126  DRPCLK => axilClk,
127  DRPDI => drpDi,
128  DRPDO => drpDo,
129  DRPEN => drpEn,
130  DRPRDY => drpRdy,
131  DRPWE => drpWe,
132  -- Clocking Ports
133  GTREFCLK0 => gtRefClk0, --address="001" for both PLLs
134  GTREFCLK1 => gtRefClk1, --address="010" for both PLLs
135  GTEASTREFCLK0 => gtEastRefClk0, --address="011" for both PLLs
136  GTEASTREFCLK1 => gtEastRefClk1, --address="100" for both PLLs
137  GTWESTREFCLK0 => gtWestRefClk0, --address="101" for both PLLs
138  GTWESTREFCLK1 => gtWestRefClk1, --address="110" for both PLLs
139  GTGREFCLK0 => gtGRefClk0, --address="111" for PLL0
140  GTGREFCLK1 => gtGRefClk1, --address="111" for PLL1
141  -- PLL0 Ports
142  PLL0OUTCLK => qPllOutClk(0),
143  PLL0OUTREFCLK => qPllOutRefClk(0),
144  PLL0FBCLKLOST => open,
145  PLL0LOCK => qPllLock(0),
146  PLL0LOCKDETCLK => qPllLockDetClk(0),
147  PLL0LOCKEN => '1',
148  PLL0PD => qPllPowerDown(0),
149  PLL0REFCLKLOST => qPllRefClkLost(0),
150  PLL0REFCLKSEL => to_stdlogicvector(PLL0_REFCLK_SEL_G),
151  PLL0RESET => qPllReset(0),
152  -- PLL1 Ports
153  PLL1OUTCLK => qPllOutClk(1),
154  PLL1OUTREFCLK => qPllOutRefClk(1),
155  PLL1FBCLKLOST => open,
156  PLL1LOCK => qPllLock(1),
157  PLL1LOCKDETCLK => qPllLockDetClk(1),
158  PLL1LOCKEN => '1',
159  PLL1PD => qPllPowerDown(1),
160  PLL1REFCLKLOST => qPllRefClkLost(1),
161  PLL1REFCLKSEL => to_stdlogicvector(PLL1_REFCLK_SEL_G),
162  PLL1RESET => qPllReset(1),
163  -- MISC Ports
164  DMONITOROUT => open,
165  BGRCALOVRDENB => '1',
166  PLLRSVD1 => "0000000000000000",
167  PLLRSVD2 => "00000",
168  REFCLKOUTMONITOR0 => open,
169  REFCLKOUTMONITOR1 => open,
170  -- RX AFE Ports -----------------------
171  PMARSVDOUT => open,
172  -- QPLL Ports
173  BGBYPASSB => '1',
174  BGMONITORENB => '1',
175  BGPDB => '1',
176  BGRCALOVRD => "00000",
177  PMARSVD => "00000000",
178  RCALENB => '1');
179 
180  U_AxiLiteToDrp : entity work.AxiLiteToDrp
181  generic map (
182  TPD_G => TPD_G,
183  AXI_ERROR_RESP_G => AXI_ERROR_RESP_G,
184  COMMON_CLK_G => true,
185  EN_ARBITRATION_G => false,
186  TIMEOUT_G => 4096,
187  ADDR_WIDTH_G => 8,
188  DATA_WIDTH_G => 16)
189  port map (
190  -- AXI-Lite Port
191  axilClk => axilClk,
192  axilRst => axilRst,
193  axilReadMaster => axilReadMaster,
194  axilReadSlave => axilReadSlave,
195  axilWriteMaster => axilWriteMaster,
196  axilWriteSlave => axilWriteSlave,
197  -- DRP Interface
198  drpClk => axilClk,
199  drpRst => axilRst,
200  drpRdy => drpRdy,
201  drpEn => drpEn,
202  drpWe => drpWe,
203  drpAddr => drpAddr,
204  drpDi => drpDi,
205  drpDo => drpDo);
206 
207 end architecture mapping;
Gtp7QuadPll.qPllRefClkLost
out qPllRefClkLostslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:50
Gtp7QuadPll.qPllRefClk
in qPllRefClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:45
AxiLiteToDrp.ADDR_WIDTH_G
ADDR_WIDTH_Gpositive range 1 to 32:= 16
Definition: AxiLiteToDrp.vhd:35
Gtp7QuadPll.PLL0_FBDIV_45_IN_G
PLL0_FBDIV_45_IN_Ginteger range 4 to 5:= 5
Definition: Gtp7QuadPll.vhd:38
Gtp7QuadPll.axilReadMaster
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: Gtp7QuadPll.vhd:56
AxiLiteToDrp.drpAddr
out drpAddrslv( ADDR_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:54
AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiLiteToDrp.EN_ARBITRATION_G
EN_ARBITRATION_Gboolean := false
Definition: AxiLiteToDrp.vhd:33
Gtp7QuadPll.qPllOutClk
out qPllOutClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:46
AxiLiteToDrp.DATA_WIDTH_G
DATA_WIDTH_Gpositive range 1 to 32:= 16
Definition: AxiLiteToDrp.vhd:36
AxiLiteToDrp.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: AxiLiteToDrp.vhd:42
Gtp7QuadPll.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Gtp7QuadPll.vhd:57
AxiLiteToDrp.drpDo
in drpDoslv( DATA_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:56
AxiLiteToDrp.COMMON_CLK_G
COMMON_CLK_Gboolean := false
Definition: AxiLiteToDrp.vhd:32
Gtp7QuadPll.PLL0_REFCLK_SEL_G
PLL0_REFCLK_SEL_Gbit_vector := "001"
Definition: Gtp7QuadPll.vhd:36
Gtp7QuadPll.qPllPowerDown
in qPllPowerDownslv( 1 downto 0) :=( others => '0')
Definition: Gtp7QuadPll.vhd:51
Gtp7QuadPll.PLL0_FBDIV_IN_G
PLL0_FBDIV_IN_Ginteger range 1 to 5:= 4
Definition: Gtp7QuadPll.vhd:37
Gtp7QuadPll.PLL0_REFCLK_DIV_IN_G
PLL0_REFCLK_DIV_IN_Ginteger range 1 to 2:= 1
Definition: Gtp7QuadPll.vhd:39
Gtp7QuadPll.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: Gtp7QuadPll.vhd:33
Gtp7QuadPll.PLL1_REFCLK_SEL_G
PLL1_REFCLK_SEL_Gbit_vector := "001"
Definition: Gtp7QuadPll.vhd:40
AxiLiteToDrp.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: AxiLiteToDrp.vhd:44
Gtp7QuadPll.PLL1_REFCLK_DIV_IN_G
PLL1_REFCLK_DIV_IN_Ginteger range 1 to 2:= 1
Definition: Gtp7QuadPll.vhd:43
AxiLitePkg.AXI_RESP_DECERR_C
slv( 1 downto 0) := "11" AXI_RESP_DECERR_C
Definition: AxiLitePkg.vhd:49
AxiLiteToDrp.axilReadMaster
in axilReadMasterAxiLiteReadMasterType
Definition: AxiLiteToDrp.vhd:41
Gtp7QuadPll.SIM_RESET_SPEEDUP_G
SIM_RESET_SPEEDUP_Gstring := "TRUE"
Definition: Gtp7QuadPll.vhd:34
Gtp7QuadPll.axilRst
in axilRstsl := '0'
Definition: Gtp7QuadPll.vhd:55
AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59
Gtp7QuadPll.TPD_G
TPD_Gtime := 1 ns
Definition: Gtp7QuadPll.vhd:32
AxiLiteToDrp.TIMEOUT_G
TIMEOUT_Gpositive := 4096
Definition: AxiLiteToDrp.vhd:34
gtpe2_common_0_i
gtpe2_common gtpe2_common_0_igtpe2_common_0_i
Definition: Gtp7QuadPll.vhd:178
Gtp7QuadPll.mapping.drpDi
slv( 15 downto 0) drpDi
Definition: Gtp7QuadPll.vhd:77
Gtp7QuadPll.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: Gtp7QuadPll.vhd:58
Gtp7QuadPll.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Gtp7QuadPll.vhd:59
Gtp7Core.ieee
_library_ ieeeieee
Definition: Gtp7Core.vhd:18
Gtp7QuadPll.mapping.drpDo
slv( 15 downto 0) drpDo
Definition: Gtp7QuadPll.vhd:78
AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType :=(araddr =>( others => '0'),arprot =>( others => '0'),arvalid => '0',rready => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69
Gtp7QuadPll.qPllReset
in qPllResetslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:52
AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85
AxiLiteToDrp.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType
Definition: AxiLiteToDrp.vhd:43
Gtp7QuadPll.qPllLockDetClk
in qPllLockDetClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:49
AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType :=(awaddr =>( others => '0'),awprot =>( others => '0'),awvalid => '0',wdata =>( others => '0'),wstrb =>( others => '1'),wvalid => '0',bready => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125
AxiLiteToDrp.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: AxiLiteToDrp.vhd:31
AxiLiteToDrp.TPD_G
TPD_Gtime := 1 ns
Definition: AxiLiteToDrp.vhd:30
Gtp7QuadPll.SIM_VERSION_G
SIM_VERSION_Gstring := "1.0"
Definition: Gtp7QuadPll.vhd:35
Gtp7QuadPll.qPllOutRefClk
out qPllOutRefClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:47
Gtp7QuadPll.axilClk
in axilClksl := '0'
Definition: Gtp7QuadPll.vhd:54
Gtp7QuadPll.PLL1_FBDIV_45_IN_G
PLL1_FBDIV_45_IN_Ginteger range 4 to 5:= 5
Definition: Gtp7QuadPll.vhd:42
Gtp7QuadPll.qPllLock
out qPllLockslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:48
Gtp7QuadPll.mapping.drpAddr
slv( 7 downto 0) drpAddr
Definition: Gtp7QuadPll.vhd:76
AxiLiteToDrp.drpDi
out drpDislv( DATA_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:55
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
Gtp7QuadPll.PLL1_FBDIV_IN_G
PLL1_FBDIV_IN_Ginteger range 1 to 5:= 4
Definition: Gtp7QuadPll.vhd:41