SURF  1.0
AxiLiteToDrp Entity Reference
+ Inheritance diagram for AxiLiteToDrp:
+ Collaboration diagram for AxiLiteToDrp:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
COMMON_CLK_G  boolean := false
EN_ARBITRATION_G  boolean := false
TIMEOUT_G  positive := 4096
ADDR_WIDTH_G  positive range 1 to 32 := 16
DATA_WIDTH_G  positive range 1 to 32 := 16

Ports

axilClk   in sl
axilRst   in sl
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType
drpClk   in sl
drpRst   in sl
drpGnt   in sl := ' 1 '
drpReq   out sl
drpRdy   in sl
drpEn   out sl
drpWe   out sl
drpUsrRst   out sl
drpAddr   out slv ( ADDR_WIDTH_G - 1 downto 0 )
drpDi   out slv ( DATA_WIDTH_G - 1 downto 0 )
drpDo   in slv ( DATA_WIDTH_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 28 of file AxiLiteToDrp.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file AxiLiteToDrp.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 31 of file AxiLiteToDrp.vhd.

◆ COMMON_CLK_G

COMMON_CLK_G boolean := false
Generic

Definition at line 32 of file AxiLiteToDrp.vhd.

◆ EN_ARBITRATION_G

EN_ARBITRATION_G boolean := false
Generic

Definition at line 33 of file AxiLiteToDrp.vhd.

◆ TIMEOUT_G

TIMEOUT_G positive := 4096
Generic

Definition at line 34 of file AxiLiteToDrp.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G positive range 1 to 32 := 16
Generic

Definition at line 35 of file AxiLiteToDrp.vhd.

◆ DATA_WIDTH_G

DATA_WIDTH_G positive range 1 to 32 := 16
Generic

Definition at line 36 of file AxiLiteToDrp.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 39 of file AxiLiteToDrp.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 40 of file AxiLiteToDrp.vhd.

◆ axilReadMaster

Definition at line 41 of file AxiLiteToDrp.vhd.

◆ axilReadSlave

Definition at line 42 of file AxiLiteToDrp.vhd.

◆ axilWriteMaster

Definition at line 43 of file AxiLiteToDrp.vhd.

◆ axilWriteSlave

Definition at line 44 of file AxiLiteToDrp.vhd.

◆ drpClk

drpClk in sl
Port

Definition at line 46 of file AxiLiteToDrp.vhd.

◆ drpRst

drpRst in sl
Port

Definition at line 47 of file AxiLiteToDrp.vhd.

◆ drpGnt

drpGnt in sl := ' 1 '
Port

Definition at line 48 of file AxiLiteToDrp.vhd.

◆ drpReq

drpReq out sl
Port

Definition at line 49 of file AxiLiteToDrp.vhd.

◆ drpRdy

drpRdy in sl
Port

Definition at line 50 of file AxiLiteToDrp.vhd.

◆ drpEn

drpEn out sl
Port

Definition at line 51 of file AxiLiteToDrp.vhd.

◆ drpWe

drpWe out sl
Port

Definition at line 52 of file AxiLiteToDrp.vhd.

◆ drpUsrRst

drpUsrRst out sl
Port

Definition at line 53 of file AxiLiteToDrp.vhd.

◆ drpAddr

drpAddr out slv ( ADDR_WIDTH_G - 1 downto 0 )
Port

Definition at line 54 of file AxiLiteToDrp.vhd.

◆ drpDi

drpDi out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 55 of file AxiLiteToDrp.vhd.

◆ drpDo

drpDo in slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 56 of file AxiLiteToDrp.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiLiteToDrp.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiLiteToDrp.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file AxiLiteToDrp.vhd.

◆ std_logic_unsigned

Definition at line 21 of file AxiLiteToDrp.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiLiteToDrp.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiLiteToDrp.vhd.


The documentation for this class was generated from the following file: