surf_1_documentation/html/Pgp2bGtp7VarLat_8vhd_source.html

 -------------------------------------------------------------------------------
 -- File       : Pgp2bGtp7VarLat.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2013-06-29
 -- Last update: 2016-08-24
 -------------------------------------------------------------------------------
 -- Description: Gtp7 Variable Latency Wrapper
 -------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
 -- It is subject to the license terms in the LICENSE.txt file found in the
 -- top-level directory of this distribution and at:
 --    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
 -- No part of 'SLAC Firmware Standard Library', including this file,
 -- may be copied, modified, propagated, or distributed except according to
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

 use work.StdRtlPkg.all;
 use work.Pgp2bPkg.all;
 use work.AxiStreamPkg.all;
 use work.AxiLitePkg.all;

 --! @see entity
  --! @ingroup protocols_pgp_pgp2b_gtp7
 entity Pgp2bGtp7VarLat is
    generic (
       TPD_G                 : time                 := 1 ns;
       ----------------------------------------------------------------------------------------------
       -- GT Settings
       ----------------------------------------------------------------------------------------------
       -- Sim Generics
       SIM_GTRESET_SPEEDUP_G : string               := "FALSE";
       SIM_VERSION_G         : string               := "1.0";
       STABLE_CLOCK_PERIOD_G : real                 := 4.0E-9;                    --units of seconds
       -- Configure PLL
       RXOUT_DIV_G           : integer              := 2;
       TXOUT_DIV_G           : integer              := 2;
       RX_CLK25_DIV_G        : integer              := 7;      -- Set by wizard
       TX_CLK25_DIV_G        : integer              := 7;      -- Set by wizard
       PMA_RSV_G             : bit_vector           := x"00000333";               -- Set by wizard
       RX_OS_CFG_G           : bit_vector           := "0001111110000";           -- Set by wizard
       RXCDR_CFG_G           : bit_vector           := x"0000107FE206001041010";  -- Set by wizard
       RXLPM_INCM_CFG_G      : bit                  := '1';    -- Set by wizard
       RXLPM_IPCM_CFG_G      : bit                  := '0';    -- Set by wizard
       TX_PLL_G              : string               := "PLL0";
       RX_PLL_G              : string               := "PLL1";
       -- Configure Buffer usage
       TX_BUF_EN_G           : boolean              := true;
       TX_OUTCLK_SRC_G       : string               := "OUTCLKPMA";
       TX_DLY_BYPASS_G       : sl                   := '1';
       TX_PHASE_ALIGN_G      : string               := "NONE";
       TX_BUF_ADDR_MODE_G    : string               := "FULL";
       ----------------------------------------------------------------------------------------------
       -- PGP Settings
       ----------------------------------------------------------------------------------------------
       VC_INTERLEAVE_G       : integer              := 0;      -- No interleave Frames
       PAYLOAD_CNT_TOP_G     : integer              := 7;      -- Top bit for payload counter
       NUM_VC_EN_G           : integer range 1 to 4 := 4;
       AXI_ERROR_RESP_G      : slv(1 downto 0)      := AXI_RESP_DECERR_C;
       TX_ENABLE_G           : boolean              := true;   -- Enable TX direction
       RX_ENABLE_G           : boolean              := true);  -- Enable RX direction
    port (
       -- GT Clocking
       stableClk        : in  sl;        -- GT needs a stable clock to "boot up"
       gtQPllOutRefClk  : in  slv(1 downto 0);
       gtQPllOutClk     : in  slv(1 downto 0);
       gtQPllLock       : in  slv(1 downto 0);
       gtQPllRefClkLost : in  slv(1 downto 0);
       gtQPllReset      : out slv(1 downto 0);
       -- Gt Serial IO
       gtTxP            : out sl;        -- GT Serial Transmit Positive
       gtTxN            : out sl;        -- GT Serial Transmit Negative
       gtRxP            : in  sl;        -- GT Serial Receive Positive
       gtRxN            : in  sl;        -- GT Serial Receive Negative
       -- Tx Clocking
       pgpTxReset       : in  sl;
       pgpTxRecClk      : out sl;        -- recovered clock
       pgpTxClk         : in  sl;
       pgpTxMmcmReset   : out sl;
       pgpTxMmcmLocked  : in  sl                               := '1';
       -- Rx clocking
       pgpRxReset       : in  sl;
       pgpRxRecClk      : out sl;        -- recovered clock
       pgpRxClk         : in  sl;
       pgpRxMmcmReset   : out sl;
       pgpRxMmcmLocked  : in  sl                               := '1';
       -- Non VC Rx Signals
       pgpRxIn          : in  Pgp2bRxInType;
       pgpRxOut         : out Pgp2bRxOutType;
       -- Non VC Tx Signals
       pgpTxIn          : in  Pgp2bTxInType;
       pgpTxOut         : out Pgp2bTxOutType;
       -- Frame Transmit Interface - Array of 4 VCs
       pgpTxMasters     : in  AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
       pgpTxSlaves      : out AxiStreamSlaveArray(3 downto 0);
       -- Frame Receive Interface - Array of 4 VCs
       pgpRxMasters     : out AxiStreamMasterArray(3 downto 0);
       pgpRxMasterMuxed : out AxiStreamMasterType;
       pgpRxCtrl        : in  AxiStreamCtrlArray(3 downto 0);
       -- Debug Interface
       txPreCursor      : in  slv(4 downto 0)                  := (others => '0');
       txPostCursor     : in  slv(4 downto 0)                  := (others => '0');
       txDiffCtrl       : in  slv(3 downto 0)                  := "1000";
       -- AXI-Lite Interface
       axilClk          : in  sl                               := '0';
       axilRst          : in  sl                               := '0';
       axilReadMaster   : in  AxiLiteReadMasterType            := AXI_LITE_READ_MASTER_INIT_C;
       axilReadSlave    : out AxiLiteReadSlaveType;
       axilWriteMaster  : in  AxiLiteWriteMasterType           := AXI_LITE_WRITE_MASTER_INIT_C;
       axilWriteSlave   : out AxiLiteWriteSlaveType);
 end Pgp2bGtp7VarLat;

 architecture mapping of Pgp2bGtp7VarLat is

 begin

    MuliLane_Inst : entity work.Pgp2bGtp7MultiLane
       generic map (
          TPD_G                 => TPD_G,
          -- SIM Generics
          SIM_GTRESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_G,
          SIM_VERSION_G         => SIM_VERSION_G,
          STABLE_CLOCK_PERIOD_G => STABLE_CLOCK_PERIOD_G,
          -- Configure PLL
          RXOUT_DIV_G           => RXOUT_DIV_G,
          TXOUT_DIV_G           => TXOUT_DIV_G,
          RX_CLK25_DIV_G        => RX_CLK25_DIV_G,
          TX_CLK25_DIV_G        => TX_CLK25_DIV_G,
          PMA_RSV_G             => PMA_RSV_G,
          RX_OS_CFG_G           => RX_OS_CFG_G,
          RXCDR_CFG_G           => RXCDR_CFG_G,
          RXLPM_INCM_CFG_G      => RXLPM_INCM_CFG_G,
          RXLPM_IPCM_CFG_G      => RXLPM_IPCM_CFG_G,
          TX_PLL_G              => TX_PLL_G,
          RX_PLL_G              => RX_PLL_G,
          -- Configure Buffer usage
          TX_BUF_EN_G           => TX_BUF_EN_G,
          TX_OUTCLK_SRC_G       => TX_OUTCLK_SRC_G,
          TX_DLY_BYPASS_G       => TX_DLY_BYPASS_G,
          TX_PHASE_ALIGN_G      => TX_PHASE_ALIGN_G,
          TX_BUF_ADDR_MODE_G    => TX_BUF_ADDR_MODE_G,
          -- PGP Settings
          VC_INTERLEAVE_G       => VC_INTERLEAVE_G,
          PAYLOAD_CNT_TOP_G     => PAYLOAD_CNT_TOP_G,
          NUM_VC_EN_G           => NUM_VC_EN_G,
          AXI_ERROR_RESP_G      => AXI_ERROR_RESP_G,
          TX_ENABLE_G           => TX_ENABLE_G,
          RX_ENABLE_G           => RX_ENABLE_G)
       port map (
          -- GT Clocking
          stableClk           => stableClk,
          gtQPllOutRefClk     => gtQPllOutRefClk,
          gtQPllOutClk        => gtQPllOutClk,
          gtQPllLock          => gtQPllLock,
          gtQPllRefClkLost    => gtQPllRefClkLost,
          gtQPllReset         => gtQPllReset,
          -- Gt Serial IO
          gtTxP(0)            => gtTxP,
          gtTxN(0)            => gtTxN,
          gtRxP(0)            => gtRxP,
          gtRxN(0)            => gtRxN,
          -- Tx Clocking
          pgpTxReset          => pgpTxReset,
          pgpTxRecClk         => pgpTxRecClk,
          pgpTxClk            => pgpTxClk,
          pgpTxMmcmReset      => pgpTxMmcmReset,
          pgpTxMmcmLocked     => pgpTxMmcmLocked,
          -- Rx clocking
          pgpRxReset          => pgpRxReset,
          pgpRxRecClk         => pgpRxRecClk,
          pgpRxClk            => pgpRxClk,
          pgpRxMmcmReset      => pgpRxMmcmReset,
          pgpRxMmcmLocked     => pgpRxMmcmLocked,
          -- Non VC Rx Signals
          pgpRxIn             => pgpRxIn,
          pgpRxOut            => pgpRxOut,
          -- Non VC Tx Signals
          pgpTxIn             => pgpTxIn,
          pgpTxOut            => pgpTxOut,
          -- Frame Transmit Interface - Array of 4 VCs
          pgpTxMasters        => pgpTxMasters,
          pgpTxSlaves         => pgpTxSlaves,
          -- Frame Receive Interface - Array of 4 VCs
          pgpRxMasters        => pgpRxMasters,
          pgpRxMasterMuxed    => pgpRxMasterMuxed,
          pgpRxCtrl           => pgpRxCtrl,
          -- Debug Interface
          txPreCursor         => txPreCursor,
          txPostCursor        => txPostCursor,
          txDiffCtrl          => txDiffCtrl,
          -- AXI-Lite Interface
          axilClk             => axilClk,
          axilRst             => axilRst,
          axilReadMasters(0)  => axilReadMaster,
          axilReadSlaves(0)   => axilReadSlave,
          axilWriteMasters(0) => axilWriteMaster,
          axilWriteSlaves(0)  => axilWriteSlave);

 end mapping;
Pgp2bGtp7VarLat.pgpTxReset
in pgpTxResetsl
Definition: Pgp2bGtp7VarLat.vhd:79

Pgp2bGtp7MultiLane.NUM_VC_EN_G
NUM_VC_EN_Ginteger   range  1 to  4:= 4
Definition: Pgp2bGtp7MultiLane.vhd:67

AxiStreamPkg.AxiStreamSlaveArray
array(natural range <> ) of AxiStreamSlaveType   AxiStreamSlaveArray
Definition: AxiStreamPkg.vhd:58

Pgp2bGtp7VarLat.pgpTxRecClk
out pgpTxRecClksl
Definition: Pgp2bGtp7VarLat.vhd:80

Pgp2bGtp7VarLat.PMA_RSV_G
PMA_RSV_Gbit_vector  := x"00000333"
Definition: Pgp2bGtp7VarLat.vhd:43

Pgp2bGtp7MultiLane.pgpTxRecClk
out pgpTxRecClksl
Definition: Pgp2bGtp7MultiLane.vhd:86

Pgp2bGtp7MultiLane.pgpRxMasters
out pgpRxMastersAxiStreamMasterArray( 3 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:106

Pgp2bGtp7MultiLane.txPreCursor
in txPreCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGtp7MultiLane.vhd:111

Pgp2bGtp7MultiLane
Definition: Pgp2bGtp7MultiLane.vhd:32

Pgp2bGtp7VarLat.gtTxN
out gtTxNsl
Definition: Pgp2bGtp7VarLat.vhd:75

Pgp2bGtp7MultiLane.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector  := x"0000107FE206001041010"
Definition: Pgp2bGtp7MultiLane.vhd:49

Pgp2bGtp7VarLat.TX_PLL_G
TX_PLL_Gstring  :=   "PLL0"
Definition: Pgp2bGtp7VarLat.vhd:48

Pgp2bGtp7VarLat.pgpTxMmcmReset
out pgpTxMmcmResetsl
Definition: Pgp2bGtp7VarLat.vhd:82

Pgp2bGtp7MultiLane.TX_ENABLE_G
TX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGtp7MultiLane.vhd:69

Pgp2bGtp7VarLat.SIM_GTRESET_SPEEDUP_G
SIM_GTRESET_SPEEDUP_Gstring  :=   "FALSE"
Definition: Pgp2bGtp7VarLat.vhd:35

Pgp2bPkg.Pgp2bTxInType
Pgp2bTxInType
Definition: Pgp2bPkg.vhd:109

Pgp2bGtp7MultiLane.PMA_RSV_G
PMA_RSV_Gbit_vector  := x"00000333"
Definition: Pgp2bGtp7MultiLane.vhd:47

AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111

StdRtlPkg.sl
std_logic   sl
Definition: StdRtlPkg.vhd:28

Pgp2bGtp7VarLat.txPreCursor
in txPreCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGtp7VarLat.vhd:104

Pgp2bGtp7MultiLane.pgpTxMasters
in pgpTxMastersAxiStreamMasterArray( 3 downto  0)  :=( others =>   AXI_STREAM_MASTER_INIT_C)
Definition: Pgp2bGtp7MultiLane.vhd:103

Pgp2bGtp7MultiLane.pgpRxReset
in pgpRxResetsl
Definition: Pgp2bGtp7MultiLane.vhd:91

Pgp2bPkg
Definition: Pgp2bPkg.vhd:25

Pgp2bGtp7MultiLane.STABLE_CLOCK_PERIOD_G
STABLE_CLOCK_PERIOD_Greal  := 4.0E-9
Definition: Pgp2bGtp7MultiLane.vhd:41

Pgp2bGtp7VarLat.RX_CLK25_DIV_G
RX_CLK25_DIV_Ginteger  := 7
Definition: Pgp2bGtp7VarLat.vhd:41

Pgp2bGtp7VarLat.pgpRxMmcmReset
out pgpRxMmcmResetsl
Definition: Pgp2bGtp7VarLat.vhd:88

AxiStreamPkg.AXI_STREAM_MASTER_INIT_C
AxiStreamMasterType  :=(tValid  => '0',tData  =>( others => '0'),tStrb  =>( others => '1'),tKeep  =>( others => '1'),tLast  => '0',tDest  =>( others => '0'),tId  =>( others => '0'),tUser  =>( others => '0')) AXI_STREAM_MASTER_INIT_C
Definition: AxiStreamPkg.vhd:40

Pgp2bGtp7MultiLane.stableClk
in stableClksl
Definition: Pgp2bGtp7MultiLane.vhd:73

Pgp2bGtp7VarLat.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto  0)  :=   AXI_RESP_DECERR_C
Definition: Pgp2bGtp7VarLat.vhd:62

Pgp2bGtp7VarLat.stableClk
in stableClksl
Definition: Pgp2bGtp7VarLat.vhd:67

Pgp2bGtp7VarLat.STABLE_CLOCK_PERIOD_G
STABLE_CLOCK_PERIOD_Greal  := 4.0E-9
Definition: Pgp2bGtp7VarLat.vhd:37

Pgp2bGtp7MultiLane.axilRst
in axilRstsl  := '0'
Definition: Pgp2bGtp7MultiLane.vhd:116

Pgp2bGtp7VarLat.pgpRxCtrl
in pgpRxCtrlAxiStreamCtrlArray( 3 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:102

Pgp2bGtp7MultiLane.txPostCursor
in txPostCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGtp7MultiLane.vhd:112

Pgp2bGtp7VarLat.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector  := x"0000107FE206001041010"
Definition: Pgp2bGtp7VarLat.vhd:45

Pgp2bGtp7MultiLane.txDiffCtrl
in txDiffCtrlslv( 3 downto  0)  :=   "1000"
Definition: Pgp2bGtp7MultiLane.vhd:113

Pgp2bGtp7VarLat.pgpTxSlaves
out pgpTxSlavesAxiStreamSlaveArray( 3 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:98

AxiLitePkg
Definition: AxiLitePkg.vhd:24

Pgp2bGtp7MultiLane.RXLPM_IPCM_CFG_G
RXLPM_IPCM_CFG_Gbit  := '0'
Definition: Pgp2bGtp7MultiLane.vhd:51

Pgp2bGtp7MultiLane.pgpRxClk
in pgpRxClksl
Definition: Pgp2bGtp7MultiLane.vhd:93

Pgp2bGtp7VarLat.TX_DLY_BYPASS_G
TX_DLY_BYPASS_Gsl  := '1'
Definition: Pgp2bGtp7VarLat.vhd:53

Pgp2bGtp7MultiLane.pgpRxMmcmLocked
in pgpRxMmcmLockedsl
Definition: Pgp2bGtp7MultiLane.vhd:95

Pgp2bGtp7MultiLane.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector  :=   "0001111110000"
Definition: Pgp2bGtp7MultiLane.vhd:48

Pgp2bGtp7VarLat.gtQPllOutRefClk
in gtQPllOutRefClkslv( 1 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:68

Pgp2bGtp7MultiLane.SIM_GTRESET_SPEEDUP_G
SIM_GTRESET_SPEEDUP_Gstring  :=   "FALSE"
Definition: Pgp2bGtp7MultiLane.vhd:39

Pgp2bGtp7VarLat.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector  :=   "0001111110000"
Definition: Pgp2bGtp7VarLat.vhd:44

Pgp2bGtp7VarLat.pgpRxIn
in pgpRxInPgp2bRxInType
Definition: Pgp2bGtp7VarLat.vhd:91

Pgp2bGtp7MultiLane.TX_BUF_EN_G
TX_BUF_EN_Gboolean  :=   true
Definition: Pgp2bGtp7MultiLane.vhd:55

Pgp2bGtp7MultiLane.axilClk
in axilClksl  := '0'
Definition: Pgp2bGtp7MultiLane.vhd:115

Pgp2bGtp7VarLat.gtQPllOutClk
in gtQPllOutClkslv( 1 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:69

Pgp2bGtp7VarLat.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType  :=   AXI_LITE_WRITE_MASTER_INIT_C
Definition: Pgp2bGtp7VarLat.vhd:112

Pgp2bGtp7VarLat.gtQPllLock
in gtQPllLockslv( 1 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:70

Pgp2bGtp7VarLat.PAYLOAD_CNT_TOP_G
PAYLOAD_CNT_TOP_Ginteger  := 7
Definition: Pgp2bGtp7VarLat.vhd:60

Pgp2bGtp7MultiLane.pgpRxRecClk
out pgpRxRecClksl
Definition: Pgp2bGtp7MultiLane.vhd:92

Pgp2bGtp7MultiLane.TX_PHASE_ALIGN_G
TX_PHASE_ALIGN_Gstring  :=   "NONE"
Definition: Pgp2bGtp7MultiLane.vhd:58

Pgp2bGtp7MultiLane.RX_ENABLE_G
RX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGtp7MultiLane.vhd:70

Pgp2bGtp7VarLat.gtQPllRefClkLost
in gtQPllRefClkLostslv( 1 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:71

Pgp2bGtp7VarLat.VC_INTERLEAVE_G
VC_INTERLEAVE_Ginteger  := 0
Definition: Pgp2bGtp7VarLat.vhd:59

Pgp2bGtp7MultiLane.pgpRxIn
in pgpRxInPgp2bRxInType
Definition: Pgp2bGtp7MultiLane.vhd:97

Pgp2bGtp7VarLat.txDiffCtrl
in txDiffCtrlslv( 3 downto  0)  :=   "1000"
Definition: Pgp2bGtp7VarLat.vhd:106

Pgp2bGtp7VarLat.TX_ENABLE_G
TX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGtp7VarLat.vhd:63

Pgp2bPkg.Pgp2bRxInType
Pgp2bRxInType
Definition: Pgp2bPkg.vhd:55

Pgp2bGtp7VarLat.RX_PLL_G
RX_PLL_Gstring  :=   "PLL1"
Definition: Pgp2bGtp7VarLat.vhd:49

AxiStreamPkg.AxiStreamMasterType
AxiStreamMasterType
Definition: AxiStreamPkg.vhd:29

AxiLitePkg.AXI_RESP_DECERR_C
slv( 1 downto  0)  :=   "11" AXI_RESP_DECERR_C
Definition: AxiLitePkg.vhd:49

Pgp2bGtp7VarLat.TX_CLK25_DIV_G
TX_CLK25_DIV_Ginteger  := 7
Definition: Pgp2bGtp7VarLat.vhd:42

Pgp2bGtp7MultiLane.gtQPllReset
out gtQPllResetslv( 1 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:78

Pgp2bGtp7VarLat.pgpTxOut
out pgpTxOutPgp2bTxOutType
Definition: Pgp2bGtp7VarLat.vhd:95

Pgp2bGtp7MultiLane.TX_OUTCLK_SRC_G
TX_OUTCLK_SRC_Gstring  :=   "OUTCLKPMA"
Definition: Pgp2bGtp7MultiLane.vhd:56

Pgp2bGtp7MultiLane.gtQPllOutClk
in gtQPllOutClkslv( 1 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:75

Pgp2bGtp7VarLat.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Pgp2bGtp7VarLat.vhd:111

Pgp2bGtp7VarLat.pgpRxMmcmLocked
in pgpRxMmcmLockedsl  := '1'
Definition: Pgp2bGtp7VarLat.vhd:89

Pgp2bGtp7VarLat.pgpTxIn
in pgpTxInPgp2bTxInType
Definition: Pgp2bGtp7VarLat.vhd:94

Pgp2bGtp7VarLat.gtRxP
in gtRxPsl
Definition: Pgp2bGtp7VarLat.vhd:76

Pgp2bGtp7VarLat.gtRxN
in gtRxNsl
Definition: Pgp2bGtp7VarLat.vhd:77

AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59

Pgp2bGtp7MultiLane.pgpTxMmcmReset
out pgpTxMmcmResetsl
Definition: Pgp2bGtp7MultiLane.vhd:88

Pgp2bGtp7VarLat.axilRst
in axilRstsl  := '0'
Definition: Pgp2bGtp7VarLat.vhd:109

Pgp2bGtp7VarLat.RXLPM_INCM_CFG_G
RXLPM_INCM_CFG_Gbit  := '1'
Definition: Pgp2bGtp7VarLat.vhd:46

Pgp2bGtp7MultiLane.VC_INTERLEAVE_G
VC_INTERLEAVE_Ginteger  := 0
Definition: Pgp2bGtp7MultiLane.vhd:65

Pgp2bGtp7VarLat.txPostCursor
in txPostCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGtp7VarLat.vhd:105

Pgp2bGtp7VarLat.TX_BUF_ADDR_MODE_G
TX_BUF_ADDR_MODE_Gstring  :=   "FULL"
Definition: Pgp2bGtp7VarLat.vhd:55

Pgp2bGtp7VarLat.gtQPllReset
out gtQPllResetslv( 1 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:72

Pgp2bGtp7MultiLane.SIM_VERSION_G
SIM_VERSION_Gstring  :=   "1.0"
Definition: Pgp2bGtp7MultiLane.vhd:40

Pgp2bGtp7MultiLane.pgpTxReset
in pgpTxResetsl
Definition: Pgp2bGtp7MultiLane.vhd:85

Pgp2bGtp7VarLat.pgpRxOut
out pgpRxOutPgp2bRxOutType
Definition: Pgp2bGtp7VarLat.vhd:92

Pgp2bGtp7MultiLane.RXOUT_DIV_G
RXOUT_DIV_Ginteger  := 2
Definition: Pgp2bGtp7MultiLane.vhd:43

Pgp2bGtp7VarLat.pgpTxMasters
in pgpTxMastersAxiStreamMasterArray( 3 downto  0)  :=( others =>   AXI_STREAM_MASTER_INIT_C)
Definition: Pgp2bGtp7VarLat.vhd:97

AxiStreamPkg.AxiStreamCtrlArray
array(natural range <> ) of AxiStreamCtrlType   AxiStreamCtrlArray
Definition: AxiStreamPkg.vhd:120

Pgp2bGtp7VarLat.RXOUT_DIV_G
RXOUT_DIV_Ginteger  := 2
Definition: Pgp2bGtp7VarLat.vhd:39

Pgp2bGtp7VarLat.pgpRxMasters
out pgpRxMastersAxiStreamMasterArray( 3 downto  0)
Definition: Pgp2bGtp7VarLat.vhd:100

Pgp2bGtp7MultiLane.RX_PLL_G
RX_PLL_Gstring  :=   "PLL1"
Definition: Pgp2bGtp7MultiLane.vhd:53

Pgp2bGtp7MultiLane.TX_DLY_BYPASS_G
TX_DLY_BYPASS_Gsl  := '1'
Definition: Pgp2bGtp7MultiLane.vhd:57

Pgp2bGtp7VarLat.RX_ENABLE_G
RX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGtp7VarLat.vhd:64

Pgp2bGtp7MultiLane.pgpTxOut
out pgpTxOutPgp2bTxOutType
Definition: Pgp2bGtp7MultiLane.vhd:101

AxiStreamPkg.AxiStreamMasterArray
array(natural range <> ) of AxiStreamMasterType   AxiStreamMasterArray
Definition: AxiStreamPkg.vhd:49

Pgp2bGtp7VarLat.gtTxP
out gtTxPsl
Definition: Pgp2bGtp7VarLat.vhd:74

Pgp2bGtp7MultiLane.pgpRxMasterMuxed
out pgpRxMasterMuxedAxiStreamMasterType
Definition: Pgp2bGtp7MultiLane.vhd:107

Pgp2bGtp7VarLat.pgpRxRecClk
out pgpRxRecClksl
Definition: Pgp2bGtp7VarLat.vhd:86

Pgp2bGtp7MultiLane.pgpTxClk
in pgpTxClksl
Definition: Pgp2bGtp7MultiLane.vhd:87

Pgp2bGtp7MultiLane.RX_CLK25_DIV_G
RX_CLK25_DIV_Ginteger  := 7
Definition: Pgp2bGtp7MultiLane.vhd:45

Pgp2bGtp7VarLat.axilClk
in axilClksl  := '0'
Definition: Pgp2bGtp7VarLat.vhd:108

AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType  :=(araddr  =>( others => '0'),arprot  =>( others => '0'),arvalid  => '0',rready  => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69

Pgp2bGtp7MultiLane.gtQPllLock
in gtQPllLockslv( 1 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:76

Pgp2bGtp7MultiLane.pgpRxMmcmReset
out pgpRxMmcmResetsl
Definition: Pgp2bGtp7MultiLane.vhd:94

AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85

Pgp2bGtp7VarLat.TPD_G
TPD_Gtime  :=  1 ns
Definition: Pgp2bGtp7VarLat.vhd:30

Pgp2bGtp7VarLat.NUM_VC_EN_G
NUM_VC_EN_Ginteger   range  1 to  4:= 4
Definition: Pgp2bGtp7VarLat.vhd:61

AxiStreamPkg
Definition: AxiStreamPkg.vhd:25

Pgp2bGtp7MultiLane.pgpRxCtrl
in pgpRxCtrlAxiStreamCtrlArray( 3 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:108

AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType  :=(awaddr  =>( others => '0'),awprot  =>( others => '0'),awvalid  => '0',wdata  =>( others => '0'),wstrb  =>( others => '1'),wvalid  => '0',bready  => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125

Pgp2bGtp7VarLat.pgpTxMmcmLocked
in pgpTxMmcmLockedsl  := '1'
Definition: Pgp2bGtp7VarLat.vhd:83

Pgp2bGtp7MultiLane.TX_BUF_ADDR_MODE_G
TX_BUF_ADDR_MODE_Gstring  :=   "FULL"
Definition: Pgp2bGtp7MultiLane.vhd:59

Pgp2bGtp7MultiLane.TX_PLL_G
TX_PLL_Gstring  :=   "PLL0"
Definition: Pgp2bGtp7MultiLane.vhd:52

Pgp2bGtp7MultiLane.pgpRxOut
out pgpRxOutPgp2bRxOutType
Definition: Pgp2bGtp7MultiLane.vhd:98

Pgp2bGtp7MultiLane.pgpTxMmcmLocked
in pgpTxMmcmLockedsl
Definition: Pgp2bGtp7MultiLane.vhd:89

Pgp2bGtp7MultiLane.PAYLOAD_CNT_TOP_G
PAYLOAD_CNT_TOP_Ginteger  := 7
Definition: Pgp2bGtp7MultiLane.vhd:66

Pgp2bGtp7VarLat.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Pgp2bGtp7VarLat.vhd:113

Pgp2bGtp7VarLat.pgpRxMasterMuxed
out pgpRxMasterMuxedAxiStreamMasterType
Definition: Pgp2bGtp7VarLat.vhd:101

Pgp2bGtp7VarLat.pgpTxClk
in pgpTxClksl
Definition: Pgp2bGtp7VarLat.vhd:81

Pgp2bGtp7MultiLane.TX_CLK25_DIV_G
TX_CLK25_DIV_Ginteger  := 7
Definition: Pgp2bGtp7MultiLane.vhd:46

Pgp2bPkg.Pgp2bTxOutType
Pgp2bTxOutType
Definition: Pgp2bPkg.vhd:135

Pgp2bGtp7MultiLane.gtQPllRefClkLost
in gtQPllRefClkLostslv( 1 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:77

Pgp2bGtp7VarLat.axilReadMaster
in axilReadMasterAxiLiteReadMasterType  :=   AXI_LITE_READ_MASTER_INIT_C
Definition: Pgp2bGtp7VarLat.vhd:110

Pgp2bGtp7VarLat.SIM_VERSION_G
SIM_VERSION_Gstring  :=   "1.0"
Definition: Pgp2bGtp7VarLat.vhd:36

StdRtlPkg
Definition: StdRtlPkg.vhd:23

Pgp2bGtp7VarLat.RXLPM_IPCM_CFG_G
RXLPM_IPCM_CFG_Gbit  := '0'
Definition: Pgp2bGtp7VarLat.vhd:47

Pgp2bGtp7VarLat.TX_OUTCLK_SRC_G
TX_OUTCLK_SRC_Gstring  :=   "OUTCLKPMA"
Definition: Pgp2bGtp7VarLat.vhd:52

Pgp2bGtp7MultiLane.RXLPM_INCM_CFG_G
RXLPM_INCM_CFG_Gbit  := '1'
Definition: Pgp2bGtp7MultiLane.vhd:50

Pgp2bGtp7MultiLane.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto  0)  :=   AXI_RESP_DECERR_C
Definition: Pgp2bGtp7MultiLane.vhd:68

Pgp2bGtp7VarLat.TX_BUF_EN_G
TX_BUF_EN_Gboolean  :=   true
Definition: Pgp2bGtp7VarLat.vhd:51

Pgp2bGtp7MultiLane.ieee
_library_ ieeeieee
Definition: Pgp2bGtp7MultiLane.vhd:18

Pgp2bGtp7VarLat
Definition: Pgp2bGtp7VarLat.vhd:28

Pgp2bGtp7MultiLane.pgpTxIn
in pgpTxInPgp2bTxInType
Definition: Pgp2bGtp7MultiLane.vhd:100

Pgp2bGtp7MultiLane.pgpTxSlaves
out pgpTxSlavesAxiStreamSlaveArray( 3 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:104

Pgp2bGtp7VarLat.TX_PHASE_ALIGN_G
TX_PHASE_ALIGN_Gstring  :=   "NONE"
Definition: Pgp2bGtp7VarLat.vhd:54

Pgp2bPkg.Pgp2bRxOutType
Pgp2bRxOutType
Definition: Pgp2bPkg.vhd:69

AxiLitePkg.AxiLiteWriteSlaveType
AxiLiteWriteSlaveType
Definition: AxiLitePkg.vhd:144

Pgp2bGtp7VarLat.pgpRxReset
in pgpRxResetsl
Definition: Pgp2bGtp7VarLat.vhd:85

Pgp2bGtp7VarLat.pgpRxClk
in pgpRxClksl
Definition: Pgp2bGtp7VarLat.vhd:87

StdRtlPkg.slv
std_logic_vector   slv
Definition: StdRtlPkg.vhd:29

Pgp2bGtp7MultiLane.TXOUT_DIV_G
TXOUT_DIV_Ginteger  := 2
Definition: Pgp2bGtp7MultiLane.vhd:44

Pgp2bGtp7MultiLane.TPD_G
TPD_Gtime  :=  1 ns
Definition: Pgp2bGtp7MultiLane.vhd:34

Pgp2bGtp7VarLat.TXOUT_DIV_G
TXOUT_DIV_Ginteger  := 2
Definition: Pgp2bGtp7VarLat.vhd:40

Pgp2bGtp7MultiLane.gtQPllOutRefClk
in gtQPllOutRefClkslv( 1 downto  0)
Definition: Pgp2bGtp7MultiLane.vhd:74