SURF  1.0
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Pgp2bGtp7MultiLane Entity Reference
protocols » pgp » pgp2b » gtp7
+ Inheritance diagram for Pgp2bGtp7MultiLane:
+ Collaboration diagram for Pgp2bGtp7MultiLane:

Entities

rtl  architecture
 

Libraries

ieee 
UNISIM 

Use Clauses

std_logic_1164 
numeric_std 
StdRtlPkg  Package <StdRtlPkg>
Pgp2bPkg  Package <Pgp2bPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
VCOMPONENTS 

Generics

TPD_G  time := 1 ns
SIM_GTRESET_SPEEDUP_G  string := " FALSE "
SIM_VERSION_G  string := " 1.0 "
STABLE_CLOCK_PERIOD_G  real := 4 . 0E - 9
RXOUT_DIV_G  integer := 2
TXOUT_DIV_G  integer := 2
RX_CLK25_DIV_G  integer := 7
TX_CLK25_DIV_G  integer := 7
PMA_RSV_G  bit_vector := x " 00000333 "
RX_OS_CFG_G  bit_vector := " 0001111110000 "
RXCDR_CFG_G  bit_vector := x " 0000107FE206001041010 "
RXLPM_INCM_CFG_G  bit := ' 1 '
RXLPM_IPCM_CFG_G  bit := ' 0 '
TX_PLL_G  string := " PLL0 "
RX_PLL_G  string := " PLL1 "
TX_BUF_EN_G  boolean := true
TX_OUTCLK_SRC_G  string := " OUTCLKPMA "
TX_DLY_BYPASS_G  sl := ' 1 '
TX_PHASE_ALIGN_G  string := " NONE "
TX_BUF_ADDR_MODE_G  string := " FULL "
LANE_CNT_G  integer range 1 to 2 := 1
VC_INTERLEAVE_G  integer := 0
PAYLOAD_CNT_TOP_G  integer := 7
NUM_VC_EN_G  integer range 1 to 4 := 4
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
TX_ENABLE_G  boolean := true
RX_ENABLE_G  boolean := true

Ports

stableClk   in sl
gtQPllOutRefClk   in slv ( 1 downto 0 )
gtQPllOutClk   in slv ( 1 downto 0 )
gtQPllLock   in slv ( 1 downto 0 )
gtQPllRefClkLost   in slv ( 1 downto 0 )
gtQPllReset   out slv ( 1 downto 0 )
gtTxP   out slv ( ( LANE_CNT_G - 1 ) downto 0 )
gtTxN   out slv ( ( LANE_CNT_G - 1 ) downto 0 )
gtRxP   in slv ( ( LANE_CNT_G - 1 ) downto 0 )
gtRxN   in slv ( ( LANE_CNT_G - 1 ) downto 0 )
pgpTxReset   in sl
pgpTxRecClk   out sl
pgpTxClk   in sl
pgpTxMmcmReset   out sl
pgpTxMmcmLocked   in sl
pgpRxReset   in sl
pgpRxRecClk   out sl
pgpRxClk   in sl
pgpRxMmcmReset   out sl
pgpRxMmcmLocked   in sl
pgpRxIn   in Pgp2bRxInType
pgpRxOut   out Pgp2bRxOutType
pgpTxIn   in Pgp2bTxInType
pgpTxOut   out Pgp2bTxOutType
pgpTxMasters   in AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves   out AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters   out AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed   out AxiStreamMasterType
pgpRxCtrl   in AxiStreamCtrlArray ( 3 downto 0 )
txPreCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl   in slv ( 3 downto 0 ) := " 1000 "
axilClk   in sl := ' 0 '
axilRst   in sl := ' 0 '
axilReadMasters   in AxiLiteReadMasterArray ( ( LANE_CNT_G - 1 ) downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axilReadSlaves   out AxiLiteReadSlaveArray ( ( LANE_CNT_G - 1 ) downto 0 )
axilWriteMasters   in AxiLiteWriteMasterArray ( ( LANE_CNT_G - 1 ) downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axilWriteSlaves   out AxiLiteWriteSlaveArray ( ( LANE_CNT_G - 1 ) downto 0 )

Detailed Description

See also
entity

Definition at line 32 of file Pgp2bGtp7MultiLane.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file Pgp2bGtp7MultiLane.vhd.

◆ SIM_GTRESET_SPEEDUP_G

SIM_GTRESET_SPEEDUP_G string := " FALSE "
Generic

Definition at line 39 of file Pgp2bGtp7MultiLane.vhd.

◆ SIM_VERSION_G

SIM_VERSION_G string := " 1.0 "
Generic

Definition at line 40 of file Pgp2bGtp7MultiLane.vhd.

◆ STABLE_CLOCK_PERIOD_G

STABLE_CLOCK_PERIOD_G real := 4 . 0E - 9
Generic

Definition at line 41 of file Pgp2bGtp7MultiLane.vhd.

◆ RXOUT_DIV_G

RXOUT_DIV_G integer := 2
Generic

Definition at line 43 of file Pgp2bGtp7MultiLane.vhd.

◆ TXOUT_DIV_G

TXOUT_DIV_G integer := 2
Generic

Definition at line 44 of file Pgp2bGtp7MultiLane.vhd.

◆ RX_CLK25_DIV_G

RX_CLK25_DIV_G integer := 7
Generic

Definition at line 45 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_CLK25_DIV_G

TX_CLK25_DIV_G integer := 7
Generic

Definition at line 46 of file Pgp2bGtp7MultiLane.vhd.

◆ PMA_RSV_G

PMA_RSV_G bit_vector := x " 00000333 "
Generic

Definition at line 47 of file Pgp2bGtp7MultiLane.vhd.

◆ RX_OS_CFG_G

RX_OS_CFG_G bit_vector := " 0001111110000 "
Generic

Definition at line 48 of file Pgp2bGtp7MultiLane.vhd.

◆ RXCDR_CFG_G

RXCDR_CFG_G bit_vector := x " 0000107FE206001041010 "
Generic

Definition at line 49 of file Pgp2bGtp7MultiLane.vhd.

◆ RXLPM_INCM_CFG_G

RXLPM_INCM_CFG_G bit := ' 1 '
Generic

Definition at line 50 of file Pgp2bGtp7MultiLane.vhd.

◆ RXLPM_IPCM_CFG_G

RXLPM_IPCM_CFG_G bit := ' 0 '
Generic

Definition at line 51 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_PLL_G

TX_PLL_G string := " PLL0 "
Generic

Definition at line 52 of file Pgp2bGtp7MultiLane.vhd.

◆ RX_PLL_G

RX_PLL_G string := " PLL1 "
Generic

Definition at line 53 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_BUF_EN_G

TX_BUF_EN_G boolean := true
Generic

Definition at line 55 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_OUTCLK_SRC_G

TX_OUTCLK_SRC_G string := " OUTCLKPMA "
Generic

Definition at line 56 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_DLY_BYPASS_G

TX_DLY_BYPASS_G sl := ' 1 '
Generic

Definition at line 57 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_PHASE_ALIGN_G

TX_PHASE_ALIGN_G string := " NONE "
Generic

Definition at line 58 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_BUF_ADDR_MODE_G

TX_BUF_ADDR_MODE_G string := " FULL "
Generic

Definition at line 59 of file Pgp2bGtp7MultiLane.vhd.

◆ LANE_CNT_G

LANE_CNT_G integer range 1 to 2 := 1
Generic

Definition at line 61 of file Pgp2bGtp7MultiLane.vhd.

◆ VC_INTERLEAVE_G

VC_INTERLEAVE_G integer := 0
Generic

Definition at line 65 of file Pgp2bGtp7MultiLane.vhd.

◆ PAYLOAD_CNT_TOP_G

PAYLOAD_CNT_TOP_G integer := 7
Generic

Definition at line 66 of file Pgp2bGtp7MultiLane.vhd.

◆ NUM_VC_EN_G

NUM_VC_EN_G integer range 1 to 4 := 4
Generic

Definition at line 67 of file Pgp2bGtp7MultiLane.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 68 of file Pgp2bGtp7MultiLane.vhd.

◆ TX_ENABLE_G

TX_ENABLE_G boolean := true
Generic

Definition at line 69 of file Pgp2bGtp7MultiLane.vhd.

◆ RX_ENABLE_G

RX_ENABLE_G boolean := true
Generic

Definition at line 70 of file Pgp2bGtp7MultiLane.vhd.

◆ stableClk

stableClk in sl
Port

Definition at line 73 of file Pgp2bGtp7MultiLane.vhd.

◆ gtQPllOutRefClk

gtQPllOutRefClk in slv ( 1 downto 0 )
Port

Definition at line 74 of file Pgp2bGtp7MultiLane.vhd.

◆ gtQPllOutClk

gtQPllOutClk in slv ( 1 downto 0 )
Port

Definition at line 75 of file Pgp2bGtp7MultiLane.vhd.

◆ gtQPllLock

gtQPllLock in slv ( 1 downto 0 )
Port

Definition at line 76 of file Pgp2bGtp7MultiLane.vhd.

◆ gtQPllRefClkLost

gtQPllRefClkLost in slv ( 1 downto 0 )
Port

Definition at line 77 of file Pgp2bGtp7MultiLane.vhd.

◆ gtQPllReset

gtQPllReset out slv ( 1 downto 0 )
Port

Definition at line 78 of file Pgp2bGtp7MultiLane.vhd.

◆ gtTxP

gtTxP out slv ( ( LANE_CNT_G - 1 ) downto 0 )
Port

Definition at line 80 of file Pgp2bGtp7MultiLane.vhd.

◆ gtTxN

gtTxN out slv ( ( LANE_CNT_G - 1 ) downto 0 )
Port

Definition at line 81 of file Pgp2bGtp7MultiLane.vhd.

◆ gtRxP

gtRxP in slv ( ( LANE_CNT_G - 1 ) downto 0 )
Port

Definition at line 82 of file Pgp2bGtp7MultiLane.vhd.

◆ gtRxN

gtRxN in slv ( ( LANE_CNT_G - 1 ) downto 0 )
Port

Definition at line 83 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxReset

pgpTxReset in sl
Port

Definition at line 85 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxRecClk

pgpTxRecClk out sl
Port

Definition at line 86 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxClk

pgpTxClk in sl
Port

Definition at line 87 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxMmcmReset

pgpTxMmcmReset out sl
Port

Definition at line 88 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxMmcmLocked

pgpTxMmcmLocked in sl
Port

Definition at line 89 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxReset

pgpRxReset in sl
Port

Definition at line 91 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxRecClk

pgpRxRecClk out sl
Port

Definition at line 92 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxClk

pgpRxClk in sl
Port

Definition at line 93 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxMmcmReset

pgpRxMmcmReset out sl
Port

Definition at line 94 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxMmcmLocked

pgpRxMmcmLocked in sl
Port

Definition at line 95 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxIn

pgpRxIn in Pgp2bRxInType
Port

Definition at line 97 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxOut

pgpRxOut out Pgp2bRxOutType
Port

Definition at line 98 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxIn

pgpTxIn in Pgp2bTxInType
Port

Definition at line 100 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxOut

pgpTxOut out Pgp2bTxOutType
Port

Definition at line 101 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxMasters

pgpTxMasters in AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
Port

Definition at line 103 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpTxSlaves

pgpTxSlaves out AxiStreamSlaveArray ( 3 downto 0 )
Port

Definition at line 104 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxMasters

pgpRxMasters out AxiStreamMasterArray ( 3 downto 0 )
Port

Definition at line 106 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxMasterMuxed

pgpRxMasterMuxed out AxiStreamMasterType
Port

Definition at line 107 of file Pgp2bGtp7MultiLane.vhd.

◆ pgpRxCtrl

pgpRxCtrl in AxiStreamCtrlArray ( 3 downto 0 )
Port

Definition at line 108 of file Pgp2bGtp7MultiLane.vhd.

◆ txPreCursor

txPreCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 111 of file Pgp2bGtp7MultiLane.vhd.

◆ txPostCursor

txPostCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 112 of file Pgp2bGtp7MultiLane.vhd.

◆ txDiffCtrl

txDiffCtrl in slv ( 3 downto 0 ) := " 1000 "
Port

Definition at line 113 of file Pgp2bGtp7MultiLane.vhd.

◆ axilClk

axilClk in sl := ' 0 '
Port

Definition at line 115 of file Pgp2bGtp7MultiLane.vhd.

◆ axilRst

axilRst in sl := ' 0 '
Port

Definition at line 116 of file Pgp2bGtp7MultiLane.vhd.

◆ axilReadMasters

axilReadMasters in AxiLiteReadMasterArray ( ( LANE_CNT_G - 1 ) downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
Port

Definition at line 117 of file Pgp2bGtp7MultiLane.vhd.

◆ axilReadSlaves

axilReadSlaves out AxiLiteReadSlaveArray ( ( LANE_CNT_G - 1 ) downto 0 )
Port

Definition at line 118 of file Pgp2bGtp7MultiLane.vhd.

◆ axilWriteMasters

axilWriteMasters in AxiLiteWriteMasterArray ( ( LANE_CNT_G - 1 ) downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
Port

Definition at line 119 of file Pgp2bGtp7MultiLane.vhd.

◆ axilWriteSlaves

axilWriteSlaves out AxiLiteWriteSlaveArray ( ( LANE_CNT_G - 1 ) downto 0 )
Port

Definition at line 120 of file Pgp2bGtp7MultiLane.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file Pgp2bGtp7MultiLane.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file Pgp2bGtp7MultiLane.vhd.

◆ numeric_std

numeric_std
Package

Definition at line 20 of file Pgp2bGtp7MultiLane.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file Pgp2bGtp7MultiLane.vhd.

◆ Pgp2bPkg

Pgp2bPkg
Package

Definition at line 23 of file Pgp2bGtp7MultiLane.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 24 of file Pgp2bGtp7MultiLane.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 25 of file Pgp2bGtp7MultiLane.vhd.

◆ UNISIM

UNISIM
Library

Definition at line 27 of file Pgp2bGtp7MultiLane.vhd.

◆ VCOMPONENTS

VCOMPONENTS
Package

Definition at line 28 of file Pgp2bGtp7MultiLane.vhd.

The documentation for this class was generated from the following file: