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Pgp2bGtp7VarLatWrapper Entity Reference
protocols » pgp » pgp2b » gtp7
+ Inheritance diagram for Pgp2bGtp7VarLatWrapper:
+ Collaboration diagram for Pgp2bGtp7VarLatWrapper:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
Pgp2bPkg  Package <Pgp2bPkg>
AxiLitePkg  Package <AxiLitePkg>
vcomponents 

Generics

TPD_G  time := 1 ns
SIMULATION_G  boolean := false
CLKIN_PERIOD_G  real := 6 . 4
DIVCLK_DIVIDE_G  natural range 1 to 106 := 1
CLKFBOUT_MULT_F_G  real range 1 . 0 to 64 . 0 := 6 . 0
CLKOUT0_DIVIDE_F_G  real range 1 . 0 to 128 . 0 := 6 . 0
QPLL_REFCLK_SEL_G  bit_vector := " 001 "
QPLL_FBDIV_IN_G  natural range 1 to 5 := 5
QPLL_FBDIV_45_IN_G  natural range 4 to 5 := 5
QPLL_REFCLK_DIV_IN_G  natural range 1 to 2 := 1
RXOUT_DIV_G  natural := 2
TXOUT_DIV_G  natural := 2
RX_CLK25_DIV_G  natural := 5
TX_CLK25_DIV_G  natural := 5
RX_OS_CFG_G  bit_vector := " 0000010000000 "
RXCDR_CFG_G  bit_vector := x " 0001107FE206021081010 "
RXLPM_INCM_CFG_G  bit := ' 0 '
RXLPM_IPCM_CFG_G  bit := ' 1 '
RX_ENABLE_G  boolean := true
TX_ENABLE_G  boolean := true
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
PAYLOAD_CNT_TOP_G  integer := 7
VC_INTERLEAVE_G  integer := 1
NUM_VC_EN_G  integer range 1 to 4 := 4

Ports

extRst   in sl
pgpClk   out sl
pgpRst   out sl
stableClk   out sl
pgpTxIn   in Pgp2bTxInType
pgpTxOut   out Pgp2bTxOutType
pgpRxIn   in Pgp2bRxInType
pgpRxOut   out Pgp2bRxOutType
pgpTxMasters   in AxiStreamMasterArray ( 3 downto 0 )
pgpTxSlaves   out AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters   out AxiStreamMasterArray ( 3 downto 0 )
pgpRxCtrl   in AxiStreamCtrlArray ( 3 downto 0 )
gtClkP   in sl
gtClkN   in sl
gtTxP   out sl
gtTxN   out sl
gtRxP   in sl
gtRxN   in sl
txPreCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl   in slv ( 3 downto 0 ) := " 1000 "
axilClk   in sl := ' 0 '
axilRst   in sl := ' 0 '
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 33 of file Pgp2bGtp7VarLatWrapper.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 35 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ SIMULATION_G

SIMULATION_G boolean := false
Generic

Definition at line 36 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ CLKIN_PERIOD_G

CLKIN_PERIOD_G real := 6 . 4
Generic

Definition at line 38 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ DIVCLK_DIVIDE_G

DIVCLK_DIVIDE_G natural range 1 to 106 := 1
Generic

Definition at line 39 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ CLKFBOUT_MULT_F_G

CLKFBOUT_MULT_F_G real range 1 . 0 to 64 . 0 := 6 . 0
Generic

Definition at line 40 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ CLKOUT0_DIVIDE_F_G

CLKOUT0_DIVIDE_F_G real range 1 . 0 to 128 . 0 := 6 . 0
Generic

Definition at line 41 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ QPLL_REFCLK_SEL_G

QPLL_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 43 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ QPLL_FBDIV_IN_G

QPLL_FBDIV_IN_G natural range 1 to 5 := 5
Generic

Definition at line 44 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ QPLL_FBDIV_45_IN_G

QPLL_FBDIV_45_IN_G natural range 4 to 5 := 5
Generic

Definition at line 45 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ QPLL_REFCLK_DIV_IN_G

QPLL_REFCLK_DIV_IN_G natural range 1 to 2 := 1
Generic

Definition at line 46 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ RXOUT_DIV_G

RXOUT_DIV_G natural := 2
Generic

Definition at line 48 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ TXOUT_DIV_G

TXOUT_DIV_G natural := 2
Generic

Definition at line 49 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ RX_CLK25_DIV_G

RX_CLK25_DIV_G natural := 5
Generic

Definition at line 50 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ TX_CLK25_DIV_G

TX_CLK25_DIV_G natural := 5
Generic

Definition at line 51 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ RX_OS_CFG_G

RX_OS_CFG_G bit_vector := " 0000010000000 "
Generic

Definition at line 52 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ RXCDR_CFG_G

RXCDR_CFG_G bit_vector := x " 0001107FE206021081010 "
Generic

Definition at line 53 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ RXLPM_INCM_CFG_G

RXLPM_INCM_CFG_G bit := ' 0 '
Generic

Definition at line 54 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ RXLPM_IPCM_CFG_G

RXLPM_IPCM_CFG_G bit := ' 1 '
Generic

Definition at line 55 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ RX_ENABLE_G

RX_ENABLE_G boolean := true
Generic

Definition at line 57 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ TX_ENABLE_G

TX_ENABLE_G boolean := true
Generic

Definition at line 58 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 59 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ PAYLOAD_CNT_TOP_G

PAYLOAD_CNT_TOP_G integer := 7
Generic

Definition at line 60 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ VC_INTERLEAVE_G

VC_INTERLEAVE_G integer := 1
Generic

Definition at line 61 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ NUM_VC_EN_G

NUM_VC_EN_G integer range 1 to 4 := 4
Generic

Definition at line 62 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ extRst

extRst in sl
Port

Definition at line 65 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpClk

pgpClk out sl
Port

Definition at line 67 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpRst

pgpRst out sl
Port

Definition at line 68 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ stableClk

stableClk out sl
Port

Definition at line 69 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpTxIn

pgpTxIn in Pgp2bTxInType
Port

Definition at line 71 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpTxOut

pgpTxOut out Pgp2bTxOutType
Port

Definition at line 72 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpRxIn

pgpRxIn in Pgp2bRxInType
Port

Definition at line 74 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpRxOut

pgpRxOut out Pgp2bRxOutType
Port

Definition at line 75 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpTxMasters

pgpTxMasters in AxiStreamMasterArray ( 3 downto 0 )
Port

Definition at line 77 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpTxSlaves

pgpTxSlaves out AxiStreamSlaveArray ( 3 downto 0 )
Port

Definition at line 78 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpRxMasters

pgpRxMasters out AxiStreamMasterArray ( 3 downto 0 )
Port

Definition at line 80 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ pgpRxCtrl

pgpRxCtrl in AxiStreamCtrlArray ( 3 downto 0 )
Port

Definition at line 81 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ gtClkP

gtClkP in sl
Port

Definition at line 83 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ gtClkN

gtClkN in sl
Port

Definition at line 84 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ gtTxP

gtTxP out sl
Port

Definition at line 85 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ gtTxN

gtTxN out sl
Port

Definition at line 86 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ gtRxP

gtRxP in sl
Port

Definition at line 87 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ gtRxN

gtRxN in sl
Port

Definition at line 88 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ txPreCursor

txPreCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 90 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ txPostCursor

txPostCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 91 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ txDiffCtrl

txDiffCtrl in slv ( 3 downto 0 ) := " 1000 "
Port

Definition at line 92 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ axilClk

axilClk in sl := ' 0 '
Port

Definition at line 94 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ axilRst

axilRst in sl := ' 0 '
Port

Definition at line 95 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 96 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 97 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 98 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 99 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 24 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ Pgp2bPkg

Pgp2bPkg
Package

Definition at line 25 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 26 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ unisim

unisim
Library

Definition at line 28 of file Pgp2bGtp7VarLatWrapper.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 29 of file Pgp2bGtp7VarLatWrapper.vhd.

The documentation for this class was generated from the following file: