SURF  1.0
Pgp2bGtp7FixedLatWrapper.vhd
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1 -------------------------------------------------------------------------------
2 -- File : Pgp2bGtp7FixedLatWrapper.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2014-01-29
5 -- Last update: 2017-01-24
6 -------------------------------------------------------------------------------
7 -- Description: Gtp7 Fixed Latency Wrapper
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.numeric_std.all;
21 
22 use work.StdRtlPkg.all;
23 use work.Pgp2bPkg.all;
24 use work.AxiStreamPkg.all;
25 use work.AxiLitePkg.all;
26 use work.Gtp7CfgPkg.all;
27 
28 library unisim;
29 use unisim.vcomponents.all;
30 
31 --! @see entity
32  --! @ingroup protocols_pgp_pgp2b_gtp7
33 entity Pgp2bGtp7FixedLatWrapper is
34  generic (
35  TPD_G : time := 1 ns;
36  SIM_GTRESET_SPEEDUP_G : boolean := false;
37  SIM_VERSION_G : string := "1.0";
38  SIMULATION_G : boolean := false;
39  -- PGP Settings
40  VC_INTERLEAVE_G : integer := 0; -- No interleave Frames
41  PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter
42  NUM_VC_EN_G : integer range 1 to 4 := 4;
43  AXIL_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_DECERR_C;
44  AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0');
45  EXT_RST_POLARITY_G : sl := '1';
46  TX_ENABLE_G : boolean := true; -- Enable TX direction
47  RX_ENABLE_G : boolean := true; -- Enable RX direction
48  -- CM Configurations
49  TX_CM_EN_G : boolean := true;
50  TX_CM_TYPE_G : string := "MMCM";
51  TX_CM_CLKIN_PERIOD_G : real := 8.000;
52  TX_CM_DIVCLK_DIVIDE_G : natural := 8;
53  TX_CM_CLKFBOUT_MULT_F_G : real := 8.000;
54  TX_CM_CLKOUT_DIVIDE_F_G : real := 8.000;
55  RX_CM_EN_G : boolean := true;
56  RX_CM_TYPE_G : string := "MMCM";
57  RX_CM_CLKIN_PERIOD_G : real := 8.000;
58  RX_CM_DIVCLK_DIVIDE_G : natural := 8;
59  RX_CM_CLKFBOUT_MULT_F_G : real := 8.000;
60  RX_CM_CLKOUT_DIVIDE_F_G : real := 8.000;
61  -- MGT Configurations
62  PMA_RSV_G : bit_vector := x"00018480";
63  RX_OS_CFG_G : bit_vector := "0000010000000"; -- Set by wizard
64  RXCDR_CFG_G : bit_vector := x"00003000023ff40200020"; -- Set by wizard
65  RXDFEXYDEN_G : sl := '0'; -- Set by wizard
66  -- PLL and clock configurations
67  STABLE_CLK_SRC_G : string := "stableClkIn"; -- or "gtClk0" or "gtClk1"
68  TX_REFCLK_SRC_G : string := "gtClk0";
69  TX_USER_CLK_SRC_G : string := "txRefClk"; -- Could be txOutClk instead
70  RX_REFCLK_SRC_G : string := "gtClk0";
71  TX_PLL_CFG_G : Gtp7QPllCfgType := getGtp7QPllCfg(156.25e6, 3.125e9);
72  RX_PLL_CFG_G : Gtp7QPllCfgType := getGtp7QPllCfg(156.25e6, 3.125e9);
73  TX_PLL_G : string := "PLL0";
74  RX_PLL_G : string := "PLL0");
75  port (
76  -- Manual Reset
77  stableClkIn : in sl := '0';
78  extRst : in sl;
79  -- Status and Clock Signals
80  txPllLock : out sl;
81  rxPllLock : out sl;
82  -- Output internally configured clocks
83  pgpTxClkOut : out sl;
84  pgpTxRstOut : out sl;
85  pgpRxClkOut : out sl;
86  pgpRxRstOut : out sl;
87  stableClkOut : out sl;
88  -- Non VC Rx Signals
89  pgpRxIn : in Pgp2bRxInType;
90  pgpRxOut : out Pgp2bRxOutType;
91  -- Non VC Tx Signals
92  pgpTxIn : in Pgp2bTxInType;
93  pgpTxOut : out Pgp2bTxOutType;
94  -- Frame Transmit Interface - 1 Lane, Array of 4 VCs
95  pgpTxMasters : in AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
96  pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0);
97  -- Frame Receive Interface - 1 Lane, Array of 4 VCs
98  pgpRxMasters : out AxiStreamMasterArray(3 downto 0);
99  pgpRxMasterMuxed : out AxiStreamMasterType;
100  pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0);
101  -- GT Pins
102  gtgClk : in sl := '0';
103  gtClk0P : in sl := '0';
104  gtClk0N : in sl := '0';
105  gtClk1P : in sl := '0';
106  gtClk1N : in sl := '0';
107  gtTxP : out sl;
108  gtTxN : out sl;
109  gtRxP : in sl;
110  gtRxN : in sl;
111  -- Debug Interface
112  txPreCursor : in slv(4 downto 0) := (others => '0');
113  txPostCursor : in slv(4 downto 0) := (others => '0');
114  txDiffCtrl : in slv(3 downto 0) := "1000";
115  -- AXI-Lite Interface
116  axilClk : in sl := '0';
117  axilRst : in sl := '0';
118  axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
119  axilReadSlave : out AxiLiteReadSlaveType;
120  axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
121  axilWriteSlave : out AxiLiteWriteSlaveType);
122 end Pgp2bGtp7FixedLatWrapper;
123 
124 architecture rtl of Pgp2bGtp7FixedLatWrapper is
125 
126  constant PLL0_CFG_C : Gtp7QPllCfgType := ite(TX_PLL_G = "PLL0", TX_PLL_CFG_G, RX_PLL_CFG_G);
127  constant PLL1_CFG_C : Gtp7QPllCfgType := ite(TX_PLL_G = "PLL1", TX_PLL_CFG_G, RX_PLL_CFG_G);
128 
129  constant SIM_GTRESET_SPEEDUP_C : string := ite(SIM_GTRESET_SPEEDUP_G, "TRUE", "FALSE");
130 
131  signal gtClk0 : sl := '0';
132  signal gtClk0Div2 : sl;
133  signal gtClk1 : sl := '0';
134  signal gtClk1Div2 : sl;
135 
136  signal txRefClk : sl := '0';
137  signal txOutClk : sl := '0';
138  signal rxRefClk : sl := '0';
139 
140  signal stableClkRef : sl := '0';
141  signal stableClkRefG : sl := '0';
142  signal stableClk : sl := '0';
143  signal stableRst : sl := '0';
144 
145  signal pgpTxClkBase : sl;
146  signal pgpTxClk : sl;
147  signal pgpTxReset : sl;
148  signal pgpTxMmcmReset : sl;
149  signal pgpTxMmcmLocked : sl;
150 
151  signal pgpRxRecClk : sl;
152  signal pgpRxRecClkRst : sl;
153  signal pgpRxClkLoc : sl;
154  signal pgpRxReset : sl;
155  signal pgpRxMmcmReset : sl;
156  signal pgpRxMmcmLocked : sl;
157 
158  signal qPllRefClk : slv(1 downto 0) := "00";
159  signal qPllOutClk : slv(1 downto 0) := "00";
160  signal qPllOutRefClk : slv(1 downto 0) := "00";
161  signal qPllLock : slv(1 downto 0) := "00";
162  signal qPllLockDetClk : slv(1 downto 0) := "00";
163  signal qPllRefClkLost : slv(1 downto 0) := "00";
164  signal qPllReset : slv(1 downto 0) := "00";
165 
166  signal locAxilWriteMasters : AxiLiteWriteMasterArray(1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C);
167  signal locAxilWriteSlaves : AxiLiteWriteSlaveArray(1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_INIT_C);
168  signal locAxilReadMasters : AxiLiteReadMasterArray(1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C);
169  signal locAxilReadSlaves : AxiLiteReadSlaveArray(1 downto 0) := (others => AXI_LITE_READ_SLAVE_INIT_C);
170 
171 begin
172 
173 
174 
175  -------------------------------------------------------------------------------------------------
176  -- Bring in the refclocks through IBUFDS_GTE2 instances
177  -------------------------------------------------------------------------------------------------
178  BUFDS_GTE2_0_GEN : if (TX_REFCLK_SRC_G = "gtClk0" or RX_REFCLK_SRC_G = "gtClk0") generate
179  IBUFDS_GTE2_0 : IBUFDS_GTE2
180  port map (
181  I => gtClk0P,
182  IB => gtClk0N,
183  CEB => '0',
184  ODIV2 => gtClk0Div2,
185  O => gtClk0);
186  end generate;
187 
188  IBUFDS_GTE2_1_GEN : if (TX_REFCLK_SRC_G = "gtClk1" or RX_REFCLK_SRC_G = "gtClk1") generate
189  IBUFDS_GTE2_1 : IBUFDS_GTE2
190  port map (
191  I => gtClk1P,
192  IB => gtClk1N,
193  CEB => '0',
194  ODIV2 => gtClk1Div2,
195  O => gtClk1);
196  end generate;
197 
198  -------------------------------------------------------------------------------------------------
199  -- Create the stable clock and reset
200  -------------------------------------------------------------------------------------------------
201  stableClkRef <= gtClk0 when STABLE_CLK_SRC_G = "gtClk0" else
202  gtClk0Div2 when STABLE_CLK_SRC_G = "gtClk0Div2" else
203  gtClk1 when STABLE_CLK_SRC_G = "gtClk1" else
204  gtClk1Div2 when STABLE_CLK_SRC_G = "gtClk1Div2" else
205  '0';
206 
207 
208  BUFG_stableClkRef : BUFG
209  port map (
210  I => stableClkRef,
211  O => stableClkRefG);
212 
213  stableClk <= stableClkIn when STABLE_CLK_SRC_G = "stableClkIn" else
214  stableClkRefG;
215 
216 
217  -- Power Up Reset
218  PwrUpRst_Inst : entity work.PwrUpRst
219  generic map (
220  TPD_G => TPD_G,
221  SIM_SPEEDUP_G => SIMULATION_G,
222  IN_POLARITY_G => EXT_RST_POLARITY_G,
223  OUT_POLARITY_G => '1')
224  port map (
225  arst => extRst,
226  clk => stableClk,
227  rstOut => stableRst);
228 
229  -------------------------------------------------------------------------------------------------
230  -- Select the rxRefClk
231  -------------------------------------------------------------------------------------------------
232  rxRefClk <= gtClk0 when RX_REFCLK_SRC_G = "gtClk0" else
233  gtClk1 when RX_REFCLK_SRC_G = "gtClk1" else
234  gtgClk when TX_REFCLK_SRC_G = "gtgClk" else
235  '0';
236 
237  -------------------------------------------------------------------------------------------------
238  -- Select the txRefClk
239  -- Generate TX user (PGP) clock
240  -- Might want option to bypass MMCM
241  -------------------------------------------------------------------------------------------------
242  txRefClk <= gtClk0 when TX_REFCLK_SRC_G = "gtClk0" else
243  gtClk1 when TX_REFCLK_SRC_G = "gtClk1" else
244  gtgClk when TX_REFCLK_SRC_G = "gtgClk" else
245  '0';
246 
247 
248  -- pgpTxClk and stable clock might be the same
249  pgpTxClkBase <= txOutClk when TX_USER_CLK_SRC_G = "txOutClk" else
250  stableClk when STABLE_CLK_SRC_G = TX_REFCLK_SRC_G else
251  txRefClk;
252 
253  TX_CM_GEN : if (TX_CM_EN_G) generate
254  ClockManager7_TX : entity work.ClockManager7
255  generic map(
256  TPD_G => TPD_G,
257  TYPE_G => TX_CM_TYPE_G,
258  INPUT_BUFG_G => ((TX_USER_CLK_SRC_G = "txOutClk") or (TX_REFCLK_SRC_G /= STABLE_CLK_SRC_G)),
259  FB_BUFG_G => true,
260  RST_IN_POLARITY_G => '1',
261  NUM_CLOCKS_G => 1,
262  -- MMCM attributes
263  BANDWIDTH_G => "OPTIMIZED",
264  CLKIN_PERIOD_G => TX_CM_CLKIN_PERIOD_G,
265  DIVCLK_DIVIDE_G => TX_CM_DIVCLK_DIVIDE_G,
266  CLKFBOUT_MULT_F_G => TX_CM_CLKFBOUT_MULT_F_G,
267  CLKOUT0_DIVIDE_F_G => TX_CM_CLKOUT_DIVIDE_F_G,
268  CLKOUT0_RST_HOLD_G => 16)
269  port map(
270  clkIn => pgpTxClkBase,
271  rstIn => pgpTxMmcmReset,
272  clkOut(0) => pgpTxClk,
273  rstOut(0) => open,
274  locked => pgpTxMmcmLocked);
275 
276  pgpTxReset <= extRst;
277 
278  end generate TX_CM_GEN;
279 
280  NO_TX_CM_GEN : if (not TX_CM_EN_G) generate
281  PGP_TX_CLK_BUFG : if (TX_USER_CLK_SRC_G = "txOutClk") or (TX_REFCLK_SRC_G /= STABLE_CLK_SRC_G) generate
282  BUFG_pgpTxClk : BUFG
283  port map (
284  i => pgpTxClkBase,
285  o => pgpTxClk);
286 
287  RstSync_pgpTxRst : entity work.RstSync
288  generic map (
289  TPD_G => TPD_G,
290  RELEASE_DELAY_G => 16,
291  OUT_REG_RST_G => true)
292  port map (
293  clk => pgpTxClk, -- [in]
294  asyncRst => extRst, -- [in]
295  syncRst => pgpTxReset); -- [out]
296  end generate PGP_TX_CLK_BUFG;
297  NO_PGP_TX_CLK_BUFG : if (TX_USER_CLK_SRC_G /= "txOutClk") and (TX_REFCLK_SRC_G = STABLE_CLK_SRC_G) generate
298  pgpTxClk <= pgpTxClkBase;
299  pgpTxReset <= stableRst;
300  end generate;
301  end generate NO_TX_CM_GEN;
302 
303  pgpTxRstOut <= pgpTxReset;
304  pgpTxClkOut <= pgpTxClk;
305 
306  -- PGP RX Reset
307  RstSync_pgpRxRst : entity work.RstSync
308  generic map (
309  TPD_G => TPD_G,
310  RELEASE_DELAY_G => 16,
311  OUT_REG_RST_G => true)
312  port map (
313  clk => pgpRxClkLoc, -- [in]
314  asyncRst => extRst, -- [in]
315  syncRst => pgpRxReset); -- [out]
316 
317 
318  -------------------------------------------------------------------------------------------------
319  -- Determine PLL clocks
320  -------------------------------------------------------------------------------------------------
321  qPllRefClk(0) <= txRefClk when (TX_PLL_G = "PLL0") else
322  rxRefClk when (RX_PLL_G = "PLL0") else
323  '0';
324 
325  qPllRefClk(1) <= txRefClk when (TX_PLL_G = "PLL1") else
326  rxRefClk when (RX_PLL_G = "PLL1") else
327  '0';
328 
329  -- Double check this. I think the pllLockDetClk must be different from the pll refclk
330 -- qPllLockDetClk(0) <= stableClk when ((TX_PLL_G = "PLL0") or (RX_PLL_G = "PLL0")) else '0';
331 -- qPllLockDetClk(1) <= stableClk when ((TX_PLL_G = "PLL1") or (RX_PLL_G = "PLL1")) else '0';
332  qPllLockDetClk(0) <= '0';
333  qPllLockDetClk(1) <= '0';
334 
335  -- Set the status outputs
336  txPllLock <= ite((TX_PLL_G = "PLL0"), qPllLock(0), qPllLock(1));
337  rxPllLock <= ite((RX_PLL_G = "PLL0"), qPllLock(0), qPllLock(1));
338 
339 
340  U_Gtp7QuadPll_1 : entity work.Gtp7QuadPll
341  generic map (
342  TPD_G => TPD_G,
343  AXI_ERROR_RESP_G => AXIL_ERROR_RESP_G,
344  SIM_RESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_C,
345  SIM_VERSION_G => SIM_VERSION_G,
346  PLL0_REFCLK_SEL_G => "001",
347  PLL0_FBDIV_IN_G => PLL0_CFG_C.QPLL_FBDIV_G,
348  PLL0_FBDIV_45_IN_G => PLL0_CFG_C.QPLL_FBDIV_45_G,
349  PLL0_REFCLK_DIV_IN_G => PLL0_CFG_C.QPLL_REFCLK_DIV_G,
350  PLL1_REFCLK_SEL_G => "001",
351  PLL1_FBDIV_IN_G => PLL1_CFG_C.QPLL_FBDIV_G,
352  PLL1_FBDIV_45_IN_G => PLL1_CFG_C.QPLL_FBDIV_45_G,
353  PLL1_REFCLK_DIV_IN_G => PLL1_CFG_C.QPLL_REFCLK_DIV_G)
354  port map (
355  qPllRefClk => qPllRefClk, -- [in]
356  qPllOutClk => qPllOutClk, -- [out]
357  qPllOutRefClk => qPllOutRefClk, -- [out]
358  qPllLock => qPllLock, -- [out]
359  qPllLockDetClk => qPllLockDetClk, -- [in]
360  qPllRefClkLost => open, -- [out]
361  qPllReset => qPllReset, -- [in]
362  axilClk => axilClk, -- [in]
363  axilRst => axilRst, -- [in]
364  axilReadMaster => locAxilReadMasters(1), -- [in]
365  axilReadSlave => locAxilReadSlaves(1), -- [out]
366  axilWriteMaster => locAxilWriteMasters(1), -- [in]
367  axilWriteSlave => locAxilWriteSlaves(1)); -- [out]
368 
369 
370  Pgp2bGtp7Fixedlat_Inst : entity work.Pgp2bGtp7FixedLat
371  generic map (
372  TPD_G => TPD_G,
373  SIM_GTRESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_C,
374  SIM_VERSION_G => SIM_VERSION_G,
375  SIMULATION_G => SIMULATION_G,
376  STABLE_CLOCK_PERIOD_G => 4.0E-9, --set for longest timeout
377  RXOUT_DIV_G => RX_PLL_CFG_G.OUT_DIV_G,
378  TXOUT_DIV_G => TX_PLL_CFG_G.OUT_DIV_G,
379  RX_CLK25_DIV_G => 7, --RX_PLL_CFG_G.CLK25_DIV_G,
380  TX_CLK25_DIV_G => 7, --TX_PLL_CFG_G.CLK25_DIV_G,
381  PMA_RSV_G => PMA_RSV_G,
382  RX_OS_CFG_G => RX_OS_CFG_G,
383  RXCDR_CFG_G => RXCDR_CFG_G,
384  TX_BUF_EN_G => true,
385  TX_OUTCLK_SRC_G => ite(TX_USER_CLK_SRC_G = "txOutClk", "OUTCLKPMA", "PLLREFCLK"),
386  TX_PHASE_ALIGN_G => "MANUAL",
387  TX_PLL_G => TX_PLL_G,
388  RX_PLL_G => RX_PLL_G,
389  VC_INTERLEAVE_G => VC_INTERLEAVE_G,
390  PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G,
391  NUM_VC_EN_G => NUM_VC_EN_G,
392  AXI_ERROR_RESP_G => AXIL_ERROR_RESP_G,
393  TX_ENABLE_G => TX_ENABLE_G,
394  RX_ENABLE_G => RX_ENABLE_G)
395  port map (
396  -- GT Clocking
397  stableClk => stableClk,
398  gtQPllOutRefClk => qPllOutRefClk,
399  gtQPllOutClk => qPllOutClk,
400  gtQPllLock => qPllLock,
401  gtQPllRefClkLost => qPllRefClkLost,
402  gtQPllReset => qPllReset,
403  gtRxRefClkBufg => '0', -- Probably can remove this
404  gtTxOutClk => txOutClk,
405  -- Gt Serial IO
406  gtTxP => gtTxP,
407  gtTxN => gtTxN,
408  gtRxP => gtRxP,
409  gtRxN => gtRxN,
410  -- Tx Clocking
411  pgpTxReset => pgpTxReset,
412  pgpTxClk => pgpTxClk,
413  pgpTxMmcmReset => pgpTxMmcmReset,
414  pgpTxMmcmLocked => pgpTxMmcmLocked,
415 
416  -- Rx clocking
417  pgpRxReset => pgpRxReset, --extRst,
418  pgpRxRecClk => pgpRxRecClk,
419  pgpRxRecClkRst => pgpRxRecClkRst,
420  pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally though MMCM
421  pgpRxMmcmReset => pgpRxMmcmReset,
422  pgpRxMmcmLocked => pgpRxMmcmLocked,
423  -- Non VC Rx Signals
424  pgpRxIn => pgpRxIn,
425  pgpRxOut => pgpRxOut,
426  -- Non VC Tx Signals
427  pgpTxIn => pgpTxIn,
428  pgpTxOut => pgpTxOut,
429  -- Frame Transmit Interface - 1 Lane, Array of 4 VCs
430  pgpTxMasters => pgpTxMasters,
431  pgpTxSlaves => pgpTxSlaves,
432  -- Frame Receive Interface - 1 Lane, Array of 4 VCs
433  pgpRxMasters => pgpRxMasters,
434  pgpRxMasterMuxed => pgpRxMasterMuxed,
435  pgpRxCtrl => pgpRxCtrl,
436  -- Debug Interface
437  txPreCursor => txPreCursor,
438  txPostCursor => txPostCursor,
439  txDiffCtrl => txDiffCtrl,
440  -- AXI-Lite Interface
441  axilClk => axilClk,
442  axilRst => axilRst,
443  axilReadMaster => locAxilReadMasters(0),
444  axilReadSlave => locAxilReadSlaves(0),
445  axilWriteMaster => locAxilWriteMasters(0),
446  axilWriteSlave => locAxilWriteSlaves(0));
447 
448  -------------------------------------------------------------------------------------------------
449  -- Clock manager to clean up recovered clock
450  -------------------------------------------------------------------------------------------------
451  RxClkMmcmGen : if (RX_CM_EN_G) generate
452  ClockManager7_1 : entity work.ClockManager7
453  generic map (
454  TPD_G => TPD_G,
455  TYPE_G => RX_CM_TYPE_G,
456  INPUT_BUFG_G => false,
457  FB_BUFG_G => true,
458  NUM_CLOCKS_G => 1,
459  BANDWIDTH_G => "HIGH",
460  CLKIN_PERIOD_G => RX_CM_CLKIN_PERIOD_G,
461  DIVCLK_DIVIDE_G => RX_CM_DIVCLK_DIVIDE_G,
462  CLKFBOUT_MULT_F_G => RX_CM_CLKFBOUT_MULT_F_G,
463  CLKOUT0_DIVIDE_F_G => RX_CM_CLKOUT_DIVIDE_F_G,
464  CLKOUT0_RST_HOLD_G => 16)
465  port map (
466  clkIn => pgpRxRecClk,
467  rstIn => pgpRxMmcmReset,
468  clkOut(0) => pgpRxClkLoc,
469  locked => pgpRxMmcmLocked);
470 
471  -- I think this is right, sync reset to mmcm clk
472  RstSync_1 : entity work.RstSync
473  generic map (
474  TPD_G => TPD_G)
475  port map (
476  clk => pgpRxClkLoc,
477  asyncRst => pgpRxRecClkRst,
478  syncRst => pgpRxRstOut);
479  end generate RxClkMmcmGen;
480 
481  RxClkNoMmcmGen : if (not RX_CM_EN_G) generate
482  pgpRxClkLoc <= pgpRxRecClk;
483  pgpRxRstOut <= pgpRxRecClkRst;
484  pgpRxMmcmLocked <= '1';
485  end generate RxClkNoMmcmGen;
486 
487  pgpRxClkOut <= pgpRxClkLoc;
488 
489  stableClkOut <= stableClk;
490 
491  -------------------------------------------------------------------------------------------------
492  -- AXI-Lite crossbar
493  -------------------------------------------------------------------------------------------------
494  U_AxiLiteCrossbar_1 : entity work.AxiLiteCrossbar
495  generic map (
496  TPD_G => TPD_G,
497  NUM_SLAVE_SLOTS_G => 1,
498  NUM_MASTER_SLOTS_G => 2,
499  DEC_ERROR_RESP_G => AXIL_ERROR_RESP_G,
500  MASTERS_CONFIG_G => genAxiLiteConfig(2, AXIL_BASE_ADDR_G, 16, 12),
501  DEBUG_G => true)
502  port map (
503  axiClk => axilClk, -- [in]
504  axiClkRst => axilRst, -- [in]
505  sAxiWriteMasters(0) => axilWriteMaster, -- [in]
506  sAxiWriteSlaves(0) => axilWriteSlave, -- [out]
507  sAxiReadMasters(0) => axilReadMaster, -- [in]
508  sAxiReadSlaves(0) => axilReadSlave, -- [out]
509  mAxiWriteMasters => locAxilWriteMasters, -- [out]
510  mAxiWriteSlaves => locAxilWriteSlaves, -- [in]
511  mAxiReadMasters => locAxilReadMasters, -- [out]
512  mAxiReadSlaves => locAxilReadSlaves); -- [in]
513 
514 end rtl;
Gtp7QuadPll.qPllRefClkLost
out qPllRefClkLostslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:50
Pgp2bGtp7FixedLatWrapper.PMA_RSV_G
PMA_RSV_Gbit_vector := x"00018480"
Definition: Pgp2bGtp7FixedLatWrapper.vhd:62
Pgp2bGtp7FixedLatWrapper.axilReadMaster
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: Pgp2bGtp7FixedLatWrapper.vhd:118
Gtp7QuadPll.qPllRefClk
in qPllRefClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:45
Pgp2bGtp7FixedLat.pgpTxMasters
in pgpTxMastersAxiStreamMasterArray( 3 downto 0) :=( others => AXI_STREAM_MASTER_INIT_C)
Definition: Pgp2bGtp7FixedLat.vhd:112
AxiLiteCrossbar.mAxiWriteSlaves
in mAxiWriteSlavesAxiLiteWriteSlaveArray( NUM_MASTER_SLOTS_G- 1 downto 0)
Definition: AxiLiteCrossbar.vhd:50
AxiStreamPkg.AxiStreamSlaveArray
array(natural range <> ) of AxiStreamSlaveType AxiStreamSlaveArray
Definition: AxiStreamPkg.vhd:58
Pgp2bGtp7FixedLat.pgpTxMmcmLocked
in pgpTxMmcmLockedsl := '1'
Definition: Pgp2bGtp7FixedLat.vhd:93
Gtp7QuadPll.PLL0_FBDIV_45_IN_G
PLL0_FBDIV_45_IN_Ginteger range 4 to 5:= 5
Definition: Gtp7QuadPll.vhd:38
PwrUpRst.rstOut
out rstOutsl
Definition: PwrUpRst.vhd:39
PwrUpRst.TPD_G
TPD_Gtime := 1 ns
Definition: PwrUpRst.vhd:30
RstSync.syncRst
out syncRstsl
Definition: RstSync.vhd:36
Pgp2bGtp7FixedLatWrapper.TX_USER_CLK_SRC_G
TX_USER_CLK_SRC_Gstring := "txRefClk"
Definition: Pgp2bGtp7FixedLatWrapper.vhd:69
AxiLitePkg.AxiLiteWriteSlaveArray
array(natural range <> ) of AxiLiteWriteSlaveType AxiLiteWriteSlaveArray
Definition: AxiLitePkg.vhd:164
Gtp7QuadPll.axilReadMaster
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: Gtp7QuadPll.vhd:56
Pgp2bGtp7FixedLat.gtQPllLock
in gtQPllLockslv( 1 downto 0) := "00"
Definition: Pgp2bGtp7FixedLat.vhd:77
AxiLiteCrossbar.mAxiReadSlaves
in mAxiReadSlavesAxiLiteReadSlaveArray( NUM_MASTER_SLOTS_G- 1 downto 0)
Definition: AxiLiteCrossbar.vhd:54
Pgp2bGtp7FixedLat.SIMULATION_G
SIMULATION_Gboolean := false
Definition: Pgp2bGtp7FixedLat.vhd:41
Pgp2bGtp7FixedLatWrapper.pgpTxSlaves
out pgpTxSlavesAxiStreamSlaveArray( 3 downto 0)
Definition: Pgp2bGtp7FixedLatWrapper.vhd:96
Pgp2bGtp7FixedLat.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector := "0001111110000"
Definition: Pgp2bGtp7FixedLat.vhd:50
Pgp2bGtp7FixedLat.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Pgp2bGtp7FixedLat.vhd:130
AxiLiteCrossbar.TPD_G
TPD_Gtime := 1 ns
Definition: AxiLiteCrossbar.vhd:32
AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiLiteCrossbar.NUM_SLAVE_SLOTS_G
NUM_SLAVE_SLOTS_Gnatural range 1 to 16:= 4
Definition: AxiLiteCrossbar.vhd:33
PwrUpRst.IN_POLARITY_G
IN_POLARITY_Gsl := '1'
Definition: PwrUpRst.vhd:32
Gtp7QuadPll.qPllOutClk
out qPllOutClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:46
AxiStreamPkg.AXI_STREAM_MASTER_INIT_C
AxiStreamMasterType :=(tValid => '0',tData =>( others => '0'),tStrb =>( others => '1'),tKeep =>( others => '1'),tLast => '0',tDest =>( others => '0'),tId =>( others => '0'),tUser =>( others => '0')) AXI_STREAM_MASTER_INIT_C
Definition: AxiStreamPkg.vhd:40
Pgp2bGtp7FixedLat.pgpRxCtrl
in pgpRxCtrlAxiStreamCtrlArray( 3 downto 0)
Definition: Pgp2bGtp7FixedLat.vhd:118
Pgp2bGtp7FixedLat.pgpRxMasterMuxed
out pgpRxMasterMuxedAxiStreamMasterType
Definition: Pgp2bGtp7FixedLat.vhd:117
Gtp7QuadPll.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Gtp7QuadPll.vhd:57
Pgp2bGtp7FixedLatWrapper.TX_PLL_CFG_G
TX_PLL_CFG_GGtp7QPllCfgType := getGtp7QPllCfg( 156.25e6, 3.125e9)
Definition: Pgp2bGtp7FixedLatWrapper.vhd:71
ClockManager7.CLKIN_PERIOD_G
CLKIN_PERIOD_Greal := 10.0
Definition: ClockManager7.vhd:44
Pgp2bGtp7FixedLatWrapper.NUM_VC_EN_G
NUM_VC_EN_Ginteger range 1 to 4:= 4
Definition: Pgp2bGtp7FixedLatWrapper.vhd:42
Pgp2bGtp7FixedLatWrapper.pgpRxMasters
out pgpRxMastersAxiStreamMasterArray( 3 downto 0)
Definition: Pgp2bGtp7FixedLatWrapper.vhd:98
Pgp2bGtp7FixedLat.pgpTxIn
in pgpTxInPgp2bTxInType
Definition: Pgp2bGtp7FixedLat.vhd:108
Pgp2bGtp7FixedLat.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: Pgp2bGtp7FixedLat.vhd:129
AxiLitePkg.AxiLiteReadMasterArray
array(natural range <> ) of AxiLiteReadMasterType AxiLiteReadMasterArray
Definition: AxiLitePkg.vhd:77
Pgp2bGtp7FixedLat.txPostCursor
in txPostCursorslv( 4 downto 0) :=( others => '0')
Definition: Pgp2bGtp7FixedLat.vhd:122
Gtp7QuadPll.PLL0_REFCLK_SEL_G
PLL0_REFCLK_SEL_Gbit_vector := "001"
Definition: Gtp7QuadPll.vhd:36
Pgp2bGtp7FixedLatWrapper.txPreCursor
in txPreCursorslv( 4 downto 0) :=( others => '0')
Definition: Pgp2bGtp7FixedLatWrapper.vhd:112
Pgp2bGtp7FixedLat.TX_CLK25_DIV_G
TX_CLK25_DIV_Ginteger := 5
Definition: Pgp2bGtp7FixedLat.vhd:48
Pgp2bGtp7FixedLat.pgpRxOut
out pgpRxOutPgp2bRxOutType
Definition: Pgp2bGtp7FixedLat.vhd:105
ClockManager7.RST_IN_POLARITY_G
RST_IN_POLARITY_Gsl := '1'
Definition: ClockManager7.vhd:39
Pgp2bGtp7FixedLat.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector := x"0000107FE206001041010"
Definition: Pgp2bGtp7FixedLat.vhd:51
Pgp2bGtp7FixedLat.pgpTxMmcmReset
out pgpTxMmcmResetsl := '0'
Definition: Pgp2bGtp7FixedLat.vhd:92
Gtp7QuadPll.PLL0_FBDIV_IN_G
PLL0_FBDIV_IN_Ginteger range 1 to 5:= 4
Definition: Gtp7QuadPll.vhd:37
Pgp2bGtp7FixedLat.txPreCursor
in txPreCursorslv( 4 downto 0) :=( others => '0')
Definition: Pgp2bGtp7FixedLat.vhd:121
AxiLiteCrossbar.DEBUG_G
DEBUG_Gboolean := false
Definition: AxiLiteCrossbar.vhd:37
ClockManager7.rstIn
in rstInsl := '0'
Definition: ClockManager7.vhd:86
Gtp7QuadPll.PLL0_REFCLK_DIV_IN_G
PLL0_REFCLK_DIV_IN_Ginteger range 1 to 2:= 1
Definition: Gtp7QuadPll.vhd:39
Pgp2bGtp7FixedLat.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: Pgp2bGtp7FixedLat.vhd:69
RstSync.asyncRst
in asyncRstsl
Definition: RstSync.vhd:35
ClockManager7.TPD_G
TPD_Gtime := 1 ns
Definition: ClockManager7.vhd:34
Pgp2bGtp7FixedLatWrapper.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Pgp2bGtp7FixedLatWrapper.vhd:121
Gtp7QuadPll.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: Gtp7QuadPll.vhd:33
Gtp7QuadPll.PLL1_REFCLK_SEL_G
PLL1_REFCLK_SEL_Gbit_vector := "001"
Definition: Gtp7QuadPll.vhd:40
Pgp2bGtp7FixedLatWrapper.AXIL_ERROR_RESP_G
AXIL_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: Pgp2bGtp7FixedLatWrapper.vhd:43
Pgp2bGtp7FixedLat.gtQPllRefClkLost
in gtQPllRefClkLostslv( 1 downto 0) := "00"
Definition: Pgp2bGtp7FixedLat.vhd:78
ClockManager7.INPUT_BUFG_G
INPUT_BUFG_Gboolean := true
Definition: ClockManager7.vhd:36
RstSync.clk
in clksl
Definition: RstSync.vhd:34
Pgp2bGtp7FixedLat.PAYLOAD_CNT_TOP_G
PAYLOAD_CNT_TOP_Ginteger := 7
Definition: Pgp2bGtp7FixedLat.vhd:67
Pgp2bGtp7FixedLatWrapper.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector := x"00003000023ff40200020"
Definition: Pgp2bGtp7FixedLatWrapper.vhd:64
PwrUpRst.arst
in arstsl :=not IN_POLARITY_G
Definition: PwrUpRst.vhd:37
Pgp2bGtp7FixedLat.PMA_RSV_G
PMA_RSV_Gbit_vector := x"00000333"
Definition: Pgp2bGtp7FixedLat.vhd:49
Pgp2bGtp7FixedLat.pgpRxIn
in pgpRxInPgp2bRxInType
Definition: Pgp2bGtp7FixedLat.vhd:104
AxiLiteCrossbar.MASTERS_CONFIG_G
MASTERS_CONFIG_GAxiLiteCrossbarMasterConfigArray := AXIL_XBAR_CFG_DEFAULT_C
Definition: AxiLiteCrossbar.vhd:36
Pgp2bPkg.Pgp2bRxInType
Pgp2bRxInType
Definition: Pgp2bPkg.vhd:55
Pgp2bGtp7FixedLat.SIM_GTRESET_SPEEDUP_G
SIM_GTRESET_SPEEDUP_Gstring := "FALSE"
Definition: Pgp2bGtp7FixedLat.vhd:39
RstSync.RELEASE_DELAY_G
RELEASE_DELAY_Ginteger range 3 to positive'high:= 3
Definition: RstSync.vhd:31
AxiLiteCrossbar.DEC_ERROR_RESP_G
DEC_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: AxiLiteCrossbar.vhd:35
Gtp7QuadPll.PLL1_REFCLK_DIV_IN_G
PLL1_REFCLK_DIV_IN_Ginteger range 1 to 2:= 1
Definition: Gtp7QuadPll.vhd:43
AxiLitePkg.AXI_RESP_DECERR_C
slv( 1 downto 0) := "11" AXI_RESP_DECERR_C
Definition: AxiLitePkg.vhd:49
Pgp2bGtp7FixedLat.TX_PLL_G
TX_PLL_Gstring := "PLL0"
Definition: Pgp2bGtp7FixedLat.vhd:60
ClockManager7.FB_BUFG_G
FB_BUFG_Gboolean := true
Definition: ClockManager7.vhd:37
Pgp2bGtp7FixedLat.TX_ENABLE_G
TX_ENABLE_Gboolean := true
Definition: Pgp2bGtp7FixedLat.vhd:70
Gtp7QuadPll.SIM_RESET_SPEEDUP_G
SIM_RESET_SPEEDUP_Gstring := "TRUE"
Definition: Gtp7QuadPll.vhd:34
Pgp2bGtp7FixedLatWrapper.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector := "0000010000000"
Definition: Pgp2bGtp7FixedLatWrapper.vhd:63
ClockManager7.BANDWIDTH_G
BANDWIDTH_Gstring := "OPTIMIZED"
Definition: ClockManager7.vhd:43
Pgp2bGtp7FixedLatWrapper.RX_PLL_CFG_G
RX_PLL_CFG_GGtp7QPllCfgType := getGtp7QPllCfg( 156.25e6, 3.125e9)
Definition: Pgp2bGtp7FixedLatWrapper.vhd:72
Gtp7QuadPll.axilRst
in axilRstsl := '0'
Definition: Gtp7QuadPll.vhd:55
AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59
Pgp2bGtp7FixedLat.TX_BUF_EN_G
TX_BUF_EN_Gboolean := false
Definition: Pgp2bGtp7FixedLat.vhd:56
ClockManager7.CLKFBOUT_MULT_F_G
CLKFBOUT_MULT_F_Greal range 1.0 to 64.0:= 1.0
Definition: ClockManager7.vhd:46
Pgp2bGtp7FixedLat.TX_PHASE_ALIGN_G
TX_PHASE_ALIGN_Gstring := "MANUAL"
Definition: Pgp2bGtp7FixedLat.vhd:58
Pgp2bGtp7FixedLat.gtQPllOutRefClk
in gtQPllOutRefClkslv( 1 downto 0) := "00"
Definition: Pgp2bGtp7FixedLat.vhd:75
ClockManager7.DIVCLK_DIVIDE_G
DIVCLK_DIVIDE_Ginteger range 1 to 106:= 1
Definition: ClockManager7.vhd:45
Pgp2bGtp7FixedLatWrapper.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Pgp2bGtp7FixedLatWrapper.vhd:119
ClockManager7.CLKOUT0_RST_HOLD_G
CLKOUT0_RST_HOLD_Ginteger range 3 to positive'high:= 3
Definition: ClockManager7.vhd:70
AxiLiteCrossbar.mAxiReadMasters
out mAxiReadMastersAxiLiteReadMasterArray( NUM_MASTER_SLOTS_G- 1 downto 0)
Definition: AxiLiteCrossbar.vhd:51
RstSync.TPD_G
TPD_Gtime := 1 ns
Definition: RstSync.vhd:27
Gtp7QuadPll.TPD_G
TPD_Gtime := 1 ns
Definition: Gtp7QuadPll.vhd:32
AxiStreamPkg.AxiStreamCtrlArray
array(natural range <> ) of AxiStreamCtrlType AxiStreamCtrlArray
Definition: AxiStreamPkg.vhd:120
Pgp2bGtp7FixedLatWrapper.txPostCursor
in txPostCursorslv( 4 downto 0) :=( others => '0')
Definition: Pgp2bGtp7FixedLatWrapper.vhd:113
Pgp2bGtp7FixedLatWrapper.txDiffCtrl
in txDiffCtrlslv( 3 downto 0) := "1000"
Definition: Pgp2bGtp7FixedLatWrapper.vhd:114
Pgp2bGtp7FixedLat.SIM_VERSION_G
SIM_VERSION_Gstring := "1.0"
Definition: Pgp2bGtp7FixedLat.vhd:40
AxiLitePkg.AXI_LITE_READ_SLAVE_INIT_C
AxiLiteReadSlaveType :=(arready => '0',rdata =>( others => '0'),rresp =>( others => '0'),rvalid => '0') AXI_LITE_READ_SLAVE_INIT_C
Definition: AxiLitePkg.vhd:95
Pgp2bGtp7FixedLat.TX_OUTCLK_SRC_G
TX_OUTCLK_SRC_Gstring := "PLLREFCLK"
Definition: Pgp2bGtp7FixedLat.vhd:57
PwrUpRst.OUT_POLARITY_G
OUT_POLARITY_Gsl := '1'
Definition: PwrUpRst.vhd:33
PwrUpRst.clk
in clksl
Definition: PwrUpRst.vhd:38
AxiStreamPkg.AxiStreamMasterArray
array(natural range <> ) of AxiStreamMasterType AxiStreamMasterArray
Definition: AxiStreamPkg.vhd:49
Pgp2bGtp7FixedLatWrapper.pgpRxMasterMuxed
out pgpRxMasterMuxedAxiStreamMasterType
Definition: Pgp2bGtp7FixedLatWrapper.vhd:99
AxiLiteCrossbar.NUM_MASTER_SLOTS_G
NUM_MASTER_SLOTS_Gnatural range 1 to 64:= 4
Definition: AxiLiteCrossbar.vhd:34
Pgp2bGtp7FixedLat.gtQPllOutClk
in gtQPllOutClkslv( 1 downto 0) := "00"
Definition: Pgp2bGtp7FixedLat.vhd:76
Gtp7QuadPll.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: Gtp7QuadPll.vhd:58
Gtp7QuadPll.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Gtp7QuadPll.vhd:59
AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType :=(araddr =>( others => '0'),arprot =>( others => '0'),arvalid => '0',rready => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69
Gtp7QuadPll.qPllReset
in qPllResetslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:52
Pgp2bGtp7FixedLat.RX_PLL_G
RX_PLL_Gstring := "PLL1"
Definition: Pgp2bGtp7FixedLat.vhd:61
RstSync.OUT_REG_RST_G
OUT_REG_RST_Gboolean := true
Definition: RstSync.vhd:32
AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85
Pgp2bGtp7FixedLat.NUM_VC_EN_G
NUM_VC_EN_Ginteger range 1 to 4:= 4
Definition: Pgp2bGtp7FixedLat.vhd:68
AxiLitePkg.AxiLiteWriteMasterArray
array(natural range <> ) of AxiLiteWriteMasterType AxiLiteWriteMasterArray
Definition: AxiLitePkg.vhd:136
Pgp2bGtp7FixedLatWrapper.pgpRxCtrl
in pgpRxCtrlAxiStreamCtrlArray( 3 downto 0)
Definition: Pgp2bGtp7FixedLatWrapper.vhd:100
Pgp2bGtp7FixedLatWrapper.AXIL_BASE_ADDR_G
AXIL_BASE_ADDR_Gslv( 31 downto 0) :=( others => '0')
Definition: Pgp2bGtp7FixedLatWrapper.vhd:44
ClockManager7.CLKOUT0_DIVIDE_F_G
CLKOUT0_DIVIDE_F_Greal range 1.0 to 128.0:= 1.0
Definition: ClockManager7.vhd:48
Gtp7QuadPll.qPllLockDetClk
in qPllLockDetClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:49
AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType :=(awaddr =>( others => '0'),awprot =>( others => '0'),awvalid => '0',wdata =>( others => '0'),wstrb =>( others => '1'),wvalid => '0',bready => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125
Pgp2bGtp7FixedLat.RX_ENABLE_G
RX_ENABLE_Gboolean := true
Definition: Pgp2bGtp7FixedLat.vhd:71
Pgp2bGtp7FixedLat.pgpRxMmcmLocked
in pgpRxMmcmLockedsl := '1'
Definition: Pgp2bGtp7FixedLat.vhd:101
Gtp7QuadPll.SIM_VERSION_G
SIM_VERSION_Gstring := "1.0"
Definition: Gtp7QuadPll.vhd:35
Pgp2bGtp7FixedLat.STABLE_CLOCK_PERIOD_G
STABLE_CLOCK_PERIOD_Greal := 4.0E-9
Definition: Pgp2bGtp7FixedLat.vhd:42
Pgp2bGtp7FixedLat.txDiffCtrl
in txDiffCtrlslv( 3 downto 0) := "1000"
Definition: Pgp2bGtp7FixedLat.vhd:123
Gtp7QuadPll.qPllOutRefClk
out qPllOutRefClkslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:47
Pgp2bGtp7FixedLat.gtQPllReset
out gtQPllResetslv( 1 downto 0)
Definition: Pgp2bGtp7FixedLat.vhd:79
Pgp2bPkg.Pgp2bTxOutType
Pgp2bTxOutType
Definition: Pgp2bPkg.vhd:135
Pgp2bGtp7FixedLat.VC_INTERLEAVE_G
VC_INTERLEAVE_Ginteger := 0
Definition: Pgp2bGtp7FixedLat.vhd:66
AxiLitePkg.AxiLiteReadSlaveArray
array(natural range <> ) of AxiLiteReadSlaveType AxiLiteReadSlaveArray
Definition: AxiLitePkg.vhd:103
Pgp2bGtp7FixedLat.axilReadMaster
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: Pgp2bGtp7FixedLat.vhd:127
Pgp2bGtp7FixedLat.pgpRxMasters
out pgpRxMastersAxiStreamMasterArray( 3 downto 0)
Definition: Pgp2bGtp7FixedLat.vhd:116
Gtp7QuadPll.axilClk
in axilClksl := '0'
Definition: Gtp7QuadPll.vhd:54
Gtp7QuadPll.PLL1_FBDIV_45_IN_G
PLL1_FBDIV_45_IN_Ginteger range 4 to 5:= 5
Definition: Gtp7QuadPll.vhd:42
AxiLiteCrossbar.mAxiWriteMasters
out mAxiWriteMastersAxiLiteWriteMasterArray( NUM_MASTER_SLOTS_G- 1 downto 0)
Definition: AxiLiteCrossbar.vhd:49
Pgp2bGtp7FixedLat.pgpTxSlaves
out pgpTxSlavesAxiStreamSlaveArray( 3 downto 0)
Definition: Pgp2bGtp7FixedLat.vhd:113
Pgp2bGtp7FixedLatWrapper.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: Pgp2bGtp7FixedLatWrapper.vhd:120
Gtp7QuadPll.qPllLock
out qPllLockslv( 1 downto 0)
Definition: Gtp7QuadPll.vhd:48
ClockManager7.TYPE_G
TYPE_Gstring := "MMCM"
Definition: ClockManager7.vhd:35
AxiLitePkg.AXI_LITE_WRITE_SLAVE_INIT_C
AxiLiteWriteSlaveType :=(awready => '0',wready => '0',bresp =>( others => '0'),bvalid => '0') AXI_LITE_WRITE_SLAVE_INIT_C
Definition: AxiLitePkg.vhd:156
PwrUpRst.SIM_SPEEDUP_G
SIM_SPEEDUP_Gboolean := false
Definition: PwrUpRst.vhd:31
Pgp2bPkg.Pgp2bRxOutType
Pgp2bRxOutType
Definition: Pgp2bPkg.vhd:69
Pgp2bGtp7FixedLat.RX_CLK25_DIV_G
RX_CLK25_DIV_Ginteger := 5
Definition: Pgp2bGtp7FixedLat.vhd:47
Pgp2bGtp7FixedLatWrapper.pgpTxMasters
in pgpTxMastersAxiStreamMasterArray( 3 downto 0) :=( others => AXI_STREAM_MASTER_INIT_C)
Definition: Pgp2bGtp7FixedLatWrapper.vhd:95
Pgp2bGtp7FixedLatWrapper.STABLE_CLK_SRC_G
STABLE_CLK_SRC_Gstring := "stableClkIn"
Definition: Pgp2bGtp7FixedLatWrapper.vhd:67
Pgp2bGtp7FixedLat.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Pgp2bGtp7FixedLat.vhd:128
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
ClockManager7.NUM_CLOCKS_G
NUM_CLOCKS_Ginteger range 1 to 7
Definition: ClockManager7.vhd:40
Gtp7QuadPll.PLL1_FBDIV_IN_G
PLL1_FBDIV_IN_Ginteger range 1 to 5:= 4
Definition: Gtp7QuadPll.vhd:41
Pgp2bGtp7FixedLat.pgpTxOut
out pgpTxOutPgp2bTxOutType
Definition: Pgp2bGtp7FixedLat.vhd:109