SURF  1.0
Generics | Ports | Libraries | Use Clauses
PwrUpRst Entity Reference
base » general
+ Inheritance diagram for PwrUpRst:
+ Collaboration diagram for PwrUpRst:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
SIM_SPEEDUP_G  boolean := false
IN_POLARITY_G  sl := ' 1 '
OUT_POLARITY_G  sl := ' 1 '
USE_DSP48_G  string := " no "
DURATION_G  natural range 0 to ( ( 2 ** 30 ) - 1 ) := 156250000

Ports

arst   in sl := not IN_POLARITY_G
clk   in sl
rstOut   out sl

Detailed Description

See also
entity

Definition at line 28 of file PwrUpRst.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file PwrUpRst.vhd.

◆ SIM_SPEEDUP_G

SIM_SPEEDUP_G boolean := false
Generic

Definition at line 31 of file PwrUpRst.vhd.

◆ IN_POLARITY_G

IN_POLARITY_G sl := ' 1 '
Generic

Definition at line 32 of file PwrUpRst.vhd.

◆ OUT_POLARITY_G

OUT_POLARITY_G sl := ' 1 '
Generic

Definition at line 33 of file PwrUpRst.vhd.

◆ USE_DSP48_G

USE_DSP48_G string := " no "
Generic

Definition at line 34 of file PwrUpRst.vhd.

◆ DURATION_G

DURATION_G natural range 0 to ( ( 2 ** 30 ) - 1 ) := 156250000
Generic

Definition at line 35 of file PwrUpRst.vhd.

◆ arst

arst in sl := not IN_POLARITY_G
Port

Definition at line 37 of file PwrUpRst.vhd.

◆ clk

clk in sl
Port

Definition at line 38 of file PwrUpRst.vhd.

◆ rstOut

rstOut out sl
Port

Definition at line 39 of file PwrUpRst.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file PwrUpRst.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file PwrUpRst.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file PwrUpRst.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file PwrUpRst.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file PwrUpRst.vhd.

The documentation for this class was generated from the following file: