SURF  1.0
Pgp2bGthUltra.vhd
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1 -------------------------------------------------------------------------------
2 -- File : Pgp2bGthUltra.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2013-06-29
5 -- Last update: 2016-01-19
6 -------------------------------------------------------------------------------
7 -- Description:
8 -------------------------------------------------------------------------------
9 -- This file is part of 'Example Project Firmware'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'Example Project Firmware', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.numeric_std.all;
21 
22 use work.StdRtlPkg.all;
23 use work.AxiStreamPkg.all;
24 use work.Pgp2bPkg.all;
25 
26 library UNISIM;
27 use UNISIM.VCOMPONENTS.all;
28 
29 --! @see entity
30  --! @ingroup protocols_pgp_pgp2b_gthUltraScale
31 entity Pgp2bGthUltra is
32  generic (
33  TPD_G : time := 1 ns;
34  ----------------------------------------------------------------------------------------------
35  -- PGP Settings
36  ----------------------------------------------------------------------------------------------
37  PGP_RX_ENABLE_G : boolean := true;
38  PGP_TX_ENABLE_G : boolean := true;
39  PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter
40  VC_INTERLEAVE_G : integer := 0; -- Interleave Frames
41  NUM_VC_EN_G : integer range 1 to 4 := 4);
42  port (
43  -- GT Clocking
44  stableClk : in sl; -- GT needs a stable clock to "boot up"
45  stableRst : in sl;
46  gtRefClk : in sl;
47  -- Gt Serial IO
48  pgpGtTxP : out sl;
49  pgpGtTxN : out sl;
50  pgpGtRxP : in sl;
51  pgpGtRxN : in sl;
52  -- Tx Clocking
53  pgpTxReset : in sl;
54  pgpTxRecClk : out sl; -- recovered clock
55  pgpTxClk : in sl;
57  -- Rx clocking
58  pgpRxReset : in sl;
59  pgpRxRecClk : out sl; -- recovered clock
60  pgpRxClk : in sl;
62  -- Non VC Rx Signals
65  -- Non VC Tx Signals
68  -- Frame Transmit Interface - 1 Lane, Array of 4 VCs
70  pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0);
71  -- Frame Receive Interface - 1 Lane, Array of 4 VCs
74  pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0));
75 end Pgp2bGthUltra;
76 
77 architecture mapping of Pgp2bGthUltra is
78 
79  -- PgpRx Signals
80  signal gtRxUserReset : sl;
83  signal phyRxReady : sl;
84  signal phyRxInit : sl;
85 
86  -- PgpTx Signals
87  signal gtTxUserReset : sl;
89  signal phyTxReady : sl;
90 
91 begin
92 
95 
96  U_Pgp2bLane : entity work.Pgp2bLane
97  generic map (
98  LANE_CNT_G => 1,
104  port map (
105  pgpTxClk => pgpTxClk,
107  pgpTxIn => pgpTxIn,
108  pgpTxOut => pgpTxOut,
111  phyTxLanesOut(0) => phyTxLaneOut,
113  pgpRxClk => pgpRxClk,
115  pgpRxIn => pgpRxIn,
116  pgpRxOut => pgpRxOut,
119  pgpRxCtrl => pgpRxCtrl,
120  phyRxLanesOut(0) => phyRxLaneOut,
121  phyRxLanesIn(0) => phyRxLaneIn,
123  phyRxInit => phyRxInit);
124 
125  --------------------------
126  -- Wrapper for GTH IP core
127  --------------------------
128  PgpGthCoreWrapper_1 : entity work.PgpGthCoreWrapper
129  generic map (
130  TPD_G => TPD_G)
131  port map (
132  stableClk => stableClk,
133  stableRst => stableRst,
134  gtRefClk => gtRefClk,
135  gtRxP => pgpGtRxP,
136  gtRxN => pgpGtRxN,
137  gtTxP => pgpGtTxP,
138  gtTxN => pgpGtTxN,
142  rxUsrClk => pgpRxClk,
143  rxData => phyRxLaneIn.data,
144  rxDataK => phyRxLaneIn.dataK,
145  rxDispErr => phyRxLaneIn.dispErr,
146  rxDecErr => phyRxLaneIn.decErr,
147  rxPolarity => phyRxLaneOut.polarity,
150  txUsrClk => pgpTxClk,
153  txData => phyTxLaneOut.data,
154  txDataK => phyTxLaneOut.dataK,
156  loopback => pgpRxIn.loopback);
157 
158 end mapping;
PAYLOAD_CNT_TOP_Ginteger := 7
out rxDispErrslv( 1 downto 0)
in pgpRxClkRstsl := '0'
Definition: Pgp2bLane.vhd:71
Pgp2bTxPhyLaneOutType phyTxLaneOut
in pgpTxMastersAxiStreamMasterArray( 3 downto 0) :=( others => AXI_STREAM_MASTER_INIT_C)
array(natural range <> ) of AxiStreamSlaveType AxiStreamSlaveArray
TX_ENABLE_Gboolean := true
Definition: Pgp2bLane.vhd:38
in loopbackslv( 2 downto 0)
out pgpTxSlavesAxiStreamSlaveArray( 3 downto 0)
PGP_RX_ENABLE_Gboolean := true
in pgpRxInPgp2bRxInType
in pgpTxInPgp2bTxInType
out pgpTxSlavesAxiStreamSlaveArray( 3 downto 0)
Definition: Pgp2bLane.vhd:58
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiStreamMasterType :=(tValid => '0',tData =>( others => '0'),tStrb =>( others => '1'),tKeep =>( others => '1'),tLast => '0',tDest =>( others => '0'),tId =>( others => '0'),tUser =>( others => '0')) AXI_STREAM_MASTER_INIT_C
out pgpRxOutPgp2bRxOutType
out rxDecErrslv( 1 downto 0)
TPD_Gtime := 1 ns
in txDataKslv( 1 downto 0)
in pgpRxInPgp2bRxInType := PGP2B_RX_IN_INIT_C
Definition: Pgp2bLane.vhd:74
VC_INTERLEAVE_Ginteger := 1
Definition: Pgp2bLane.vhd:35
out phyRxInitsl
Definition: Pgp2bLane.vhd:89
in pgpRxMmcmLockedsl
VC_INTERLEAVE_Ginteger := 0
Pgp2bRxPhyLaneOutType
Definition: Pgp2bPkg.vhd:159
RX_ENABLE_Gboolean := true
Definition: Pgp2bLane.vhd:40
Pgp2bRxPhyLaneInType phyRxLaneIn
out pgpRxOutPgp2bRxOutType
Definition: Pgp2bLane.vhd:75
in pgpTxMastersAxiStreamMasterArray( 3 downto 0) :=( others => AXI_STREAM_MASTER_INIT_C)
Definition: Pgp2bLane.vhd:57
in phyRxReadysl := '0'
Definition: Pgp2bLane.vhd:87
NUM_VC_EN_Ginteger range 1 to 4:= 4
Definition: Pgp2bLane.vhd:37
PGP_TX_ENABLE_Gboolean := true
Pgp2bRxPhyLaneOutType phyRxLaneOut
Pgp2bRxInType
Definition: Pgp2bPkg.vhd:55
Pgp2bRxPhyLaneInType
Definition: Pgp2bPkg.vhd:167
PAYLOAD_CNT_TOP_Ginteger := 7
Definition: Pgp2bLane.vhd:36
out pgpRxRecClksl
sl resetRx
Definition: Pgp2bPkg.vhd:57
in pgpTxClkRstsl := '0'
Definition: Pgp2bLane.vhd:50
in pgpRxCtrlAxiStreamCtrlArray( 3 downto 0) :=( others => AXI_STREAM_CTRL_UNUSED_C)
Definition: Pgp2bLane.vhd:82
array(natural range <> ) of AxiStreamCtrlType AxiStreamCtrlArray
in pgpRxClksl := '0'
Definition: Pgp2bLane.vhd:70
in pgpTxMmcmLockedsl
in txDataslv( 15 downto 0)
out pgpTxOutPgp2bTxOutType
out pgpTxOutPgp2bTxOutType
Definition: Pgp2bLane.vhd:54
array(natural range <> ) of AxiStreamMasterType AxiStreamMasterArray
in pgpTxClksl := '0'
Definition: Pgp2bLane.vhd:49
LANE_CNT_Ginteger range 1 to 2:= 1
Definition: Pgp2bLane.vhd:34
NUM_VC_EN_Ginteger range 1 to 4:= 4
in pgpRxCtrlAxiStreamCtrlArray( 3 downto 0)
in pgpTxInPgp2bTxInType := PGP2B_TX_IN_INIT_C
Definition: Pgp2bLane.vhd:53
out rxDataslv( 15 downto 0)
out pgpRxMastersAxiStreamMasterArray( 3 downto 0)
Definition: Pgp2bLane.vhd:78
Pgp2bTxOutType
Definition: Pgp2bPkg.vhd:135
out rxDataKslv( 1 downto 0)
Pgp2bTxPhyLaneOutType
Definition: Pgp2bPkg.vhd:187
out pgpTxRecClksl
in phyTxReadysl := '0'
Definition: Pgp2bLane.vhd:62
Pgp2bRxOutType
Definition: Pgp2bPkg.vhd:69
out pgpRxMasterMuxedAxiStreamMasterType
out pgpRxMastersAxiStreamMasterArray( 3 downto 0)
out pgpRxMasterMuxedAxiStreamMasterType
Definition: Pgp2bLane.vhd:79