surf_1_documentation/html/Pgp2bGth7VarLatWrapper_8vhd_source.html

 -------------------------------------------------------------------------------
 -- File       : Pgp2bGth7VarLatWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -- Created    : 2015-04-01
 -- Last update: 2016-08-24
 -------------------------------------------------------------------------------
 -- Description: Example PGP 3.125 Gbps front end wrapper
 -- Note: Default generic configurations are for the Diligent NetFPGA-SUME development board
 -- Note: Default uses FPGA fabric clock = 156.25 MHz reference clock
 -------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
 -- It is subject to the license terms in the LICENSE.txt file found in the
 -- top-level directory of this distribution and at:
 --    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
 -- No part of 'SLAC Firmware Standard Library', including this file,
 -- may be copied, modified, propagated, or distributed except according to
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

 use work.StdRtlPkg.all;
 use work.AxiStreamPkg.all;
 use work.Pgp2bPkg.all;
 use work.AxiLitePkg.all;

 library unisim;
 use unisim.vcomponents.all;

 --! @see entity
  --! @ingroup protocols_pgp_pgp2b_gth7
 entity Pgp2bGth7VarLatWrapper is
    generic (
       TPD_G             : time                 := 1 ns;
       -- CPLL Configurations (Defaults: pgpClk = 156.25 MHz Configuration)
       CPLL_FBDIV_G      : natural              := 4;
       CPLL_FBDIV_45_G   : natural              := 5;
       CPLL_REFCLK_DIV_G : natural              := 1;
       -- MGT Configurations (Defaults: pgpClk = 156.25 MHz Configuration)
       RXOUT_DIV_G       : natural              := 2;
       TXOUT_DIV_G       : natural              := 2;
       RX_CLK25_DIV_G    : natural              := 7;
       TX_CLK25_DIV_G    : natural              := 7;
       RX_OS_CFG_G       : bit_vector           := "0000010000000";           -- Set by wizard
       RXCDR_CFG_G       : bit_vector           := x"0002007FE1000C2200018";  -- Set by wizard
       RXDFEXYDEN_G      : sl                   := '1';                       -- Set by wizard
       -- PGP Settings
       VC_INTERLEAVE_G   : integer              := 0;  -- No interleave Frames
       PAYLOAD_CNT_TOP_G : integer              := 7;  -- Top bit for payload counter
       NUM_VC_EN_G       : integer range 1 to 4 := 4;
       AXI_ERROR_RESP_G  : slv(1 downto 0)      := AXI_RESP_DECERR_C;
       TX_ENABLE_G       : boolean              := true;                      -- Enable TX direction
       RX_ENABLE_G       : boolean              := true);                     -- Enable RX direction
    port (
       -- Clocks and Reset
       pgpClk          : in  sl;
       pgpRst          : in  sl;
       -- Non VC TX Signals
       pgpTxIn         : in  Pgp2bTxInType;
       pgpTxOut        : out Pgp2bTxOutType;
       -- Non VC RX Signals
       pgpRxIn         : in  Pgp2bRxInType;
       pgpRxOut        : out Pgp2bRxOutType;
       -- Frame TX Interface
       pgpTxMasters    : in  AxiStreamMasterArray(3 downto 0);
       pgpTxSlaves     : out AxiStreamSlaveArray(3 downto 0);
       -- Frame RX Interface
       pgpRxMasters    : out AxiStreamMasterArray(3 downto 0);
       pgpRxCtrl       : in  AxiStreamCtrlArray(3 downto 0);
       -- GT Pins
       gtTxP           : out sl;
       gtTxN           : out sl;
       gtRxP           : in  sl;
       gtRxN           : in  sl;
       -- Debug Interface
       txPreCursor     : in  slv(4 downto 0)        := (others => '0');
       txPostCursor    : in  slv(4 downto 0)        := (others => '0');
       txDiffCtrl      : in  slv(3 downto 0)        := "1000";
       -- AXI-Lite Interface
       axilClk         : in  sl                     := '0';
       axilRst         : in  sl                     := '0';
       axilReadMaster  : in  AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
       axilReadSlave   : out AxiLiteReadSlaveType;
       axilWriteMaster : in  AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
       axilWriteSlave  : out AxiLiteWriteSlaveType);
 end Pgp2bGth7VarLatWrapper;

 architecture mapping of Pgp2bGth7VarLatWrapper is

 begin

    Pgp2bGth7VarLat_Inst : entity work.Pgp2bGth7VarLat
       generic map (
          TPD_G             => TPD_G,
          -- CPLL Configurations
          TX_PLL_G          => "CPLL",
          RX_PLL_G          => "CPLL",
          CPLL_REFCLK_SEL_G => "111",
          CPLL_FBDIV_G      => CPLL_FBDIV_G,
          CPLL_FBDIV_45_G   => CPLL_FBDIV_45_G,
          CPLL_REFCLK_DIV_G => CPLL_REFCLK_DIV_G,
          -- MGT Configurations
          RXOUT_DIV_G       => RXOUT_DIV_G,
          TXOUT_DIV_G       => TXOUT_DIV_G,
          RX_CLK25_DIV_G    => RX_CLK25_DIV_G,
          TX_CLK25_DIV_G    => TX_CLK25_DIV_G,
          RX_OS_CFG_G       => RX_OS_CFG_G,
          RXCDR_CFG_G       => RXCDR_CFG_G,
          RXDFEXYDEN_G      => RXDFEXYDEN_G,
          -- VC Configuration
          VC_INTERLEAVE_G   => VC_INTERLEAVE_G,
          PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G,
          NUM_VC_EN_G       => NUM_VC_EN_G,
          AXI_ERROR_RESP_G  => AXI_ERROR_RESP_G,
          TX_ENABLE_G       => TX_ENABLE_G,
          RX_ENABLE_G       => RX_ENABLE_G)
       port map (
          -- GT Clocking
          stableClk        => pgpClk,
          gtCPllRefClk     => pgpClk,
          gtCPllLock       => open,
          gtQPllRefClk     => '0',
          gtQPllClk        => '0',
          gtQPllLock       => '1',
          gtQPllRefClkLost => '0',
          gtQPllReset      => open,
          -- GT Serial IO
          gtTxP            => gtTxP,
          gtTxN            => gtTxN,
          gtRxP            => gtRxP,
          gtRxN            => gtRxN,
          -- Tx Clocking
          pgpTxReset       => pgpRst,
          pgpTxRecClk      => open,
          pgpTxClk         => pgpClk,
          pgpTxMmcmReset   => open,
          pgpTxMmcmLocked  => '1',
          -- Rx clocking
          pgpRxReset       => pgpRst,
          pgpRxRecClk      => open,
          pgpRxClk         => pgpClk,
          pgpRxMmcmReset   => open,
          pgpRxMmcmLocked  => '1',
          -- Non VC TX Signals
          pgpTxIn          => pgpTxIn,
          pgpTxOut         => pgpTxOut,
          -- Non VC RX Signals
          pgpRxIn          => pgpRxIn,
          pgpRxOut         => pgpRxOut,
          -- Frame TX Interface
          pgpTxMasters     => pgpTxMasters,
          pgpTxSlaves      => pgpTxSlaves,
          -- Frame RX Interface
          pgpRxMasters     => pgpRxMasters,
          pgpRxCtrl        => pgpRxCtrl,
          -- Debug Interface
          txPreCursor      => txPreCursor,
          txPostCursor     => txPostCursor,
          txDiffCtrl       => txDiffCtrl,
          -- AXI-Lite Interface
          axilClk          => axilClk,
          axilRst          => axilRst,
          axilReadMaster   => axilReadMaster,
          axilReadSlave    => axilReadSlave,
          axilWriteMaster  => axilWriteMaster,
          axilWriteSlave   => axilWriteSlave);

 end mapping;
Pgp2bGth7VarLatWrapper.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector  := x"0002007FE1000C2200018"
Definition: Pgp2bGth7VarLatWrapper.vhd:46

Pgp2bGth7VarLat.CPLL_REFCLK_SEL_G
CPLL_REFCLK_SEL_Gbit_vector  :=   "001"
Definition: Pgp2bGth7VarLat.vhd:39

Pgp2bGth7VarLat.pgpRxMasters
out pgpRxMastersAxiStreamMasterArray( 3 downto  0)
Definition: Pgp2bGth7VarLat.vhd:110

Pgp2bGth7VarLat.RXDFEXYDEN_G
RXDFEXYDEN_Gsl  := '1'
Definition: Pgp2bGth7VarLat.vhd:51

AxiStreamPkg.AxiStreamSlaveArray
array(natural range <> ) of AxiStreamSlaveType   AxiStreamSlaveArray
Definition: AxiStreamPkg.vhd:58

Pgp2bGth7VarLatWrapper.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Pgp2bGth7VarLatWrapper.vhd:84

Pgp2bGth7VarLatWrapper.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto  0)  :=   AXI_RESP_DECERR_C
Definition: Pgp2bGth7VarLatWrapper.vhd:52

Pgp2bGth7VarLat.gtQPllClk
in gtQPllClksl
Definition: Pgp2bGth7VarLat.vhd:79

Pgp2bGth7VarLatWrapper.pgpTxSlaves
out pgpTxSlavesAxiStreamSlaveArray( 3 downto  0)
Definition: Pgp2bGth7VarLatWrapper.vhd:67

Pgp2bGth7VarLatWrapper.CPLL_FBDIV_G
CPLL_FBDIV_Gnatural  := 4
Definition: Pgp2bGth7VarLatWrapper.vhd:37

Pgp2bGth7VarLatWrapper.pgpRxMasters
out pgpRxMastersAxiStreamMasterArray( 3 downto  0)
Definition: Pgp2bGth7VarLatWrapper.vhd:69

Pgp2bGth7VarLat.gtRxN
in gtRxNsl
Definition: Pgp2bGth7VarLat.vhd:87

Pgp2bGth7VarLat.stableClk
in stableClksl
Definition: Pgp2bGth7VarLat.vhd:75

Pgp2bGth7VarLat.axilRst
in axilRstsl  := '0'
Definition: Pgp2bGth7VarLat.vhd:119

Pgp2bGth7VarLatWrapper.pgpRst
in pgpRstsl
Definition: Pgp2bGth7VarLatWrapper.vhd:58

Pgp2bGth7VarLat.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType  :=   AXI_LITE_WRITE_MASTER_INIT_C
Definition: Pgp2bGth7VarLat.vhd:122

Pgp2bGth7VarLat.txPostCursor
in txPostCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGth7VarLat.vhd:115

Pgp2bGth7VarLat.pgpRxCtrl
in pgpRxCtrlAxiStreamCtrlArray( 3 downto  0)
Definition: Pgp2bGth7VarLat.vhd:112

Pgp2bPkg.Pgp2bTxInType
Pgp2bTxInType
Definition: Pgp2bPkg.vhd:109

Pgp2bGth7VarLatWrapper.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Pgp2bGth7VarLatWrapper.vhd:86

Pgp2bGth7VarLat.pgpTxReset
in pgpTxResetsl
Definition: Pgp2bGth7VarLat.vhd:89

Pgp2bGth7VarLatWrapper.VC_INTERLEAVE_G
VC_INTERLEAVE_Ginteger  := 0
Definition: Pgp2bGth7VarLatWrapper.vhd:49

AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111

StdRtlPkg.sl
std_logic   sl
Definition: StdRtlPkg.vhd:28

Pgp2bGth7VarLatWrapper.RX_ENABLE_G
RX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGth7VarLatWrapper.vhd:54

Pgp2bPkg
Definition: Pgp2bPkg.vhd:25

Pgp2bGth7VarLat.VC_INTERLEAVE_G
VC_INTERLEAVE_Ginteger  := 0
Definition: Pgp2bGth7VarLat.vhd:67

Pgp2bGth7VarLatWrapper.axilRst
in axilRstsl  := '0'
Definition: Pgp2bGth7VarLatWrapper.vhd:82

Pgp2bGth7VarLatWrapper.CPLL_REFCLK_DIV_G
CPLL_REFCLK_DIV_Gnatural  := 1
Definition: Pgp2bGth7VarLatWrapper.vhd:39

Pgp2bGth7VarLat.TX_PLL_G
TX_PLL_Gstring  :=   "QPLL"
Definition: Pgp2bGth7VarLat.vhd:54

Pgp2bGth7VarLat.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Pgp2bGth7VarLat.vhd:121

Pgp2bGth7VarLatWrapper.RXDFEXYDEN_G
RXDFEXYDEN_Gsl  := '1'
Definition: Pgp2bGth7VarLatWrapper.vhd:47

Pgp2bGth7VarLat.gtQPllLock
in gtQPllLocksl
Definition: Pgp2bGth7VarLat.vhd:80

Pgp2bGth7VarLat.pgpRxIn
in pgpRxInPgp2bRxInType
Definition: Pgp2bGth7VarLat.vhd:101

Pgp2bGth7VarLatWrapper.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType  :=   AXI_LITE_WRITE_MASTER_INIT_C
Definition: Pgp2bGth7VarLatWrapper.vhd:85

AxiLitePkg
Definition: AxiLitePkg.vhd:24

Pgp2bGth7VarLatWrapper.pgpRxOut
out pgpRxOutPgp2bRxOutType
Definition: Pgp2bGth7VarLatWrapper.vhd:64

Pgp2bGth7VarLat.TX_CLK25_DIV_G
TX_CLK25_DIV_Ginteger  := 7
Definition: Pgp2bGth7VarLat.vhd:46

Pgp2bGth7VarLatWrapper.TXOUT_DIV_G
TXOUT_DIV_Gnatural  := 2
Definition: Pgp2bGth7VarLatWrapper.vhd:42

Pgp2bGth7VarLatWrapper.pgpClk
in pgpClksl
Definition: Pgp2bGth7VarLatWrapper.vhd:57

Pgp2bGth7VarLatWrapper.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector  :=   "0000010000000"
Definition: Pgp2bGth7VarLatWrapper.vhd:45

Pgp2bGth7VarLat.pgpRxOut
out pgpRxOutPgp2bRxOutType
Definition: Pgp2bGth7VarLat.vhd:102

Pgp2bGth7VarLatWrapper.pgpTxMasters
in pgpTxMastersAxiStreamMasterArray( 3 downto  0)
Definition: Pgp2bGth7VarLatWrapper.vhd:66

Pgp2bGth7VarLatWrapper.txDiffCtrl
in txDiffCtrlslv( 3 downto  0)  :=   "1000"
Definition: Pgp2bGth7VarLatWrapper.vhd:79

Pgp2bGth7VarLat.RX_OS_CFG_G
RX_OS_CFG_Gbit_vector  :=   "0000010000000"
Definition: Pgp2bGth7VarLat.vhd:49

Pgp2bGth7VarLat.RX_PLL_G
RX_PLL_Gstring  :=   "CPLL"
Definition: Pgp2bGth7VarLat.vhd:55

Pgp2bGth7VarLat.pgpTxIn
in pgpTxInPgp2bTxInType
Definition: Pgp2bGth7VarLat.vhd:104

Pgp2bGth7VarLat.pgpRxMmcmLocked
in pgpRxMmcmLockedsl
Definition: Pgp2bGth7VarLat.vhd:99

Pgp2bGth7VarLat.txDiffCtrl
in txDiffCtrlslv( 3 downto  0)  :=   "1000"
Definition: Pgp2bGth7VarLat.vhd:116

Pgp2bGth7VarLatWrapper.gtRxN
in gtRxNsl
Definition: Pgp2bGth7VarLatWrapper.vhd:75

Pgp2bGth7VarLat.pgpTxMmcmLocked
in pgpTxMmcmLockedsl
Definition: Pgp2bGth7VarLat.vhd:93

Pgp2bGth7VarLat.PAYLOAD_CNT_TOP_G
PAYLOAD_CNT_TOP_Ginteger  := 7
Definition: Pgp2bGth7VarLat.vhd:68

Pgp2bGth7VarLatWrapper.PAYLOAD_CNT_TOP_G
PAYLOAD_CNT_TOP_Ginteger  := 7
Definition: Pgp2bGth7VarLatWrapper.vhd:50

Pgp2bGth7VarLat.RXCDR_CFG_G
RXCDR_CFG_Gbit_vector  := x"0002007FE1000C2200018"
Definition: Pgp2bGth7VarLat.vhd:50

Pgp2bGth7VarLatWrapper.pgpRxCtrl
in pgpRxCtrlAxiStreamCtrlArray( 3 downto  0)
Definition: Pgp2bGth7VarLatWrapper.vhd:70

Pgp2bGth7VarLatWrapper.pgpTxIn
in pgpTxInPgp2bTxInType
Definition: Pgp2bGth7VarLatWrapper.vhd:60

Pgp2bGth7VarLat.pgpTxMasters
in pgpTxMastersAxiStreamMasterArray( 3 downto  0)  :=( others =>   AXI_STREAM_MASTER_INIT_C)
Definition: Pgp2bGth7VarLat.vhd:107

Pgp2bPkg.Pgp2bRxInType
Pgp2bRxInType
Definition: Pgp2bPkg.vhd:55

AxiLitePkg.AXI_RESP_DECERR_C
slv( 1 downto  0)  :=   "11" AXI_RESP_DECERR_C
Definition: AxiLitePkg.vhd:49

Pgp2bGth7VarLat.gtQPllReset
out gtQPllResetsl
Definition: Pgp2bGth7VarLat.vhd:82

Pgp2bGth7VarLat.pgpTxMmcmReset
out pgpTxMmcmResetsl
Definition: Pgp2bGth7VarLat.vhd:92

Pgp2bGth7VarLat.NUM_VC_EN_G
NUM_VC_EN_Ginteger   range  1 to  4:= 4
Definition: Pgp2bGth7VarLat.vhd:69

Pgp2bGth7VarLat
Definition: Pgp2bGth7VarLat.vhd:28

Pgp2bGth7VarLatWrapper.gtRxP
in gtRxPsl
Definition: Pgp2bGth7VarLatWrapper.vhd:74

Pgp2bGth7VarLat.axilClk
in axilClksl  := '0'
Definition: Pgp2bGth7VarLat.vhd:118

Pgp2bGth7VarLat.CPLL_FBDIV_G
CPLL_FBDIV_Ginteger  := 4
Definition: Pgp2bGth7VarLat.vhd:40

Pgp2bGth7VarLat.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Pgp2bGth7VarLat.vhd:123

AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59

Pgp2bGth7VarLatWrapper.CPLL_FBDIV_45_G
CPLL_FBDIV_45_Gnatural  := 5
Definition: Pgp2bGth7VarLatWrapper.vhd:38

Pgp2bGth7VarLatWrapper.gtTxP
out gtTxPsl
Definition: Pgp2bGth7VarLatWrapper.vhd:72

Pgp2bGth7VarLatWrapper.axilReadMaster
in axilReadMasterAxiLiteReadMasterType  :=   AXI_LITE_READ_MASTER_INIT_C
Definition: Pgp2bGth7VarLatWrapper.vhd:83

Pgp2bGth7VarLatWrapper.TX_CLK25_DIV_G
TX_CLK25_DIV_Gnatural  := 7
Definition: Pgp2bGth7VarLatWrapper.vhd:44

AxiStreamPkg.AxiStreamCtrlArray
array(natural range <> ) of AxiStreamCtrlType   AxiStreamCtrlArray
Definition: AxiStreamPkg.vhd:120

Pgp2bGth7VarLat.gtQPllRefClk
in gtQPllRefClksl
Definition: Pgp2bGth7VarLat.vhd:78

Pgp2bGth7VarLat.ieee
_library_ ieeeieee
Definition: Pgp2bGth7VarLat.vhd:18

Pgp2bGth7VarLatWrapper
Definition: Pgp2bGth7VarLatWrapper.vhd:33

Pgp2bGth7VarLat.pgpTxRecClk
out pgpTxRecClksl
Definition: Pgp2bGth7VarLat.vhd:91

Pgp2bGth7VarLat.pgpRxMmcmReset
out pgpRxMmcmResetsl
Definition: Pgp2bGth7VarLat.vhd:98

Pgp2bGth7VarLat.pgpTxSlaves
out pgpTxSlavesAxiStreamSlaveArray( 3 downto  0)
Definition: Pgp2bGth7VarLat.vhd:108

AxiStreamPkg.AxiStreamMasterArray
array(natural range <> ) of AxiStreamMasterType   AxiStreamMasterArray
Definition: AxiStreamPkg.vhd:49

Pgp2bGth7VarLat.gtCPllLock
out gtCPllLocksl
Definition: Pgp2bGth7VarLat.vhd:77

Pgp2bGth7VarLat.gtTxN
out gtTxNsl
Definition: Pgp2bGth7VarLat.vhd:85

AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType  :=(araddr  =>( others => '0'),arprot  =>( others => '0'),arvalid  => '0',rready  => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69

Pgp2bGth7VarLat.TX_ENABLE_G
TX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGth7VarLat.vhd:71

Pgp2bGth7VarLat.gtRxP
in gtRxPsl
Definition: Pgp2bGth7VarLat.vhd:86

Pgp2bGth7VarLatWrapper.NUM_VC_EN_G
NUM_VC_EN_Ginteger   range  1 to  4:= 4
Definition: Pgp2bGth7VarLatWrapper.vhd:51

AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85

Pgp2bGth7VarLat.pgpTxOut
out pgpTxOutPgp2bTxOutType
Definition: Pgp2bGth7VarLat.vhd:105

AxiStreamPkg
Definition: AxiStreamPkg.vhd:25

AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType  :=(awaddr  =>( others => '0'),awprot  =>( others => '0'),awvalid  => '0',wdata  =>( others => '0'),wstrb  =>( others => '1'),wvalid  => '0',bready  => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125

Pgp2bGth7VarLat.pgpRxRecClk
out pgpRxRecClksl
Definition: Pgp2bGth7VarLat.vhd:96

Pgp2bGth7VarLat.TPD_G
TPD_Gtime  :=  1 ns
Definition: Pgp2bGth7VarLat.vhd:30

Pgp2bGth7VarLat.axilReadMaster
in axilReadMasterAxiLiteReadMasterType  :=   AXI_LITE_READ_MASTER_INIT_C
Definition: Pgp2bGth7VarLat.vhd:120

Pgp2bGth7VarLat.TXOUT_DIV_G
TXOUT_DIV_Ginteger  := 2
Definition: Pgp2bGth7VarLat.vhd:44

Pgp2bGth7VarLatWrapper.txPreCursor
in txPreCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGth7VarLatWrapper.vhd:77

Pgp2bGth7VarLatWrapper.gtTxN
out gtTxNsl
Definition: Pgp2bGth7VarLatWrapper.vhd:73

Pgp2bGth7VarLatWrapper.txPostCursor
in txPostCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGth7VarLatWrapper.vhd:78

Pgp2bPkg.Pgp2bTxOutType
Pgp2bTxOutType
Definition: Pgp2bPkg.vhd:135

Pgp2bGth7VarLat.gtTxP
out gtTxPsl
Definition: Pgp2bGth7VarLat.vhd:84

StdRtlPkg
Definition: StdRtlPkg.vhd:23

Pgp2bGth7VarLat.RX_CLK25_DIV_G
RX_CLK25_DIV_Ginteger  := 7
Definition: Pgp2bGth7VarLat.vhd:45

Pgp2bGth7VarLatWrapper.RX_CLK25_DIV_G
RX_CLK25_DIV_Gnatural  := 7
Definition: Pgp2bGth7VarLatWrapper.vhd:43

Pgp2bGth7VarLat.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto  0)  :=   AXI_RESP_DECERR_C
Definition: Pgp2bGth7VarLat.vhd:70

Pgp2bGth7VarLat.RXOUT_DIV_G
RXOUT_DIV_Ginteger  := 2
Definition: Pgp2bGth7VarLat.vhd:43

Pgp2bGth7VarLat.gtQPllRefClkLost
in gtQPllRefClkLostsl
Definition: Pgp2bGth7VarLat.vhd:81

Pgp2bGth7VarLat.CPLL_REFCLK_DIV_G
CPLL_REFCLK_DIV_Ginteger  := 1
Definition: Pgp2bGth7VarLat.vhd:42

Pgp2bGth7VarLat.RX_ENABLE_G
RX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGth7VarLat.vhd:72

Pgp2bGth7VarLatWrapper.pgpRxIn
in pgpRxInPgp2bRxInType
Definition: Pgp2bGth7VarLatWrapper.vhd:63

Pgp2bGth7VarLat.pgpRxClk
in pgpRxClksl
Definition: Pgp2bGth7VarLat.vhd:97

Pgp2bGth7VarLat.pgpTxClk
in pgpTxClksl
Definition: Pgp2bGth7VarLat.vhd:90

Pgp2bPkg.Pgp2bRxOutType
Pgp2bRxOutType
Definition: Pgp2bPkg.vhd:69

AxiLitePkg.AxiLiteWriteSlaveType
AxiLiteWriteSlaveType
Definition: AxiLitePkg.vhd:144

Pgp2bGth7VarLat.CPLL_FBDIV_45_G
CPLL_FBDIV_45_Ginteger  := 5
Definition: Pgp2bGth7VarLat.vhd:41

Pgp2bGth7VarLatWrapper.axilClk
in axilClksl  := '0'
Definition: Pgp2bGth7VarLatWrapper.vhd:81

Pgp2bGth7VarLat.gtCPllRefClk
in gtCPllRefClksl
Definition: Pgp2bGth7VarLat.vhd:76

Pgp2bGth7VarLatWrapper.TX_ENABLE_G
TX_ENABLE_Gboolean  :=   true
Definition: Pgp2bGth7VarLatWrapper.vhd:53

StdRtlPkg.slv
std_logic_vector   slv
Definition: StdRtlPkg.vhd:29

Pgp2bGth7VarLat.txPreCursor
in txPreCursorslv( 4 downto  0)  :=( others => '0')
Definition: Pgp2bGth7VarLat.vhd:114

Pgp2bGth7VarLatWrapper.pgpTxOut
out pgpTxOutPgp2bTxOutType
Definition: Pgp2bGth7VarLatWrapper.vhd:61

Pgp2bGth7VarLatWrapper.TPD_G
TPD_Gtime  :=  1 ns
Definition: Pgp2bGth7VarLatWrapper.vhd:35

Pgp2bGth7VarLatWrapper.RXOUT_DIV_G
RXOUT_DIV_Gnatural  := 2
Definition: Pgp2bGth7VarLatWrapper.vhd:41

Pgp2bGth7VarLat.pgpRxReset
in pgpRxResetsl
Definition: Pgp2bGth7VarLat.vhd:95