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Pgp2bGth7VarLat Entity Reference
protocols » pgp » pgp2b » gth7
+ Inheritance diagram for Pgp2bGth7VarLat:
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Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
Pgp2bPkg  Package <Pgp2bPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
SIM_GTRESET_SPEEDUP_G  string := " FALSE "
SIM_VERSION_G  string := " 2.0 "
STABLE_CLOCK_PERIOD_G  real := 4 . 0E - 9
CPLL_REFCLK_SEL_G  bit_vector := " 001 "
CPLL_FBDIV_G  integer := 4
CPLL_FBDIV_45_G  integer := 5
CPLL_REFCLK_DIV_G  integer := 1
RXOUT_DIV_G  integer := 2
TXOUT_DIV_G  integer := 2
RX_CLK25_DIV_G  integer := 7
TX_CLK25_DIV_G  integer := 7
PMA_RSV_G  bit_vector := x " 00000080 "
RX_OS_CFG_G  bit_vector := " 0000010000000 "
RXCDR_CFG_G  bit_vector := x " 0002007FE1000C2200018 "
RXDFEXYDEN_G  sl := ' 1 '
TX_PLL_G  string := " QPLL "
RX_PLL_G  string := " CPLL "
TX_BUF_EN_G  boolean := true
TX_OUTCLK_SRC_G  string := " OUTCLKPMA "
TX_DLY_BYPASS_G  sl := ' 1 '
TX_PHASE_ALIGN_G  string := " NONE "
TX_BUF_ADDR_MODE_G  string := " FULL "
VC_INTERLEAVE_G  integer := 0
PAYLOAD_CNT_TOP_G  integer := 7
NUM_VC_EN_G  integer range 1 to 4 := 4
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
TX_ENABLE_G  boolean := true
RX_ENABLE_G  boolean := true

Ports

stableClk   in sl
gtCPllRefClk   in sl
gtCPllLock   out sl
gtQPllRefClk   in sl
gtQPllClk   in sl
gtQPllLock   in sl
gtQPllRefClkLost   in sl
gtQPllReset   out sl
gtTxP   out sl
gtTxN   out sl
gtRxP   in sl
gtRxN   in sl
pgpTxReset   in sl
pgpTxClk   in sl
pgpTxRecClk   out sl
pgpTxMmcmReset   out sl
pgpTxMmcmLocked   in sl
pgpRxReset   in sl
pgpRxRecClk   out sl
pgpRxClk   in sl
pgpRxMmcmReset   out sl
pgpRxMmcmLocked   in sl
pgpRxIn   in Pgp2bRxInType
pgpRxOut   out Pgp2bRxOutType
pgpTxIn   in Pgp2bTxInType
pgpTxOut   out Pgp2bTxOutType
pgpTxMasters   in AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves   out AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters   out AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed   out AxiStreamMasterType
pgpRxCtrl   in AxiStreamCtrlArray ( 3 downto 0 )
txPreCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl   in slv ( 3 downto 0 ) := " 1000 "
axilClk   in sl := ' 0 '
axilRst   in sl := ' 0 '
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 28 of file Pgp2bGth7VarLat.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file Pgp2bGth7VarLat.vhd.

◆ SIM_GTRESET_SPEEDUP_G

SIM_GTRESET_SPEEDUP_G string := " FALSE "
Generic

Definition at line 35 of file Pgp2bGth7VarLat.vhd.

◆ SIM_VERSION_G

SIM_VERSION_G string := " 2.0 "
Generic

Definition at line 36 of file Pgp2bGth7VarLat.vhd.

◆ STABLE_CLOCK_PERIOD_G

STABLE_CLOCK_PERIOD_G real := 4 . 0E - 9
Generic

Definition at line 37 of file Pgp2bGth7VarLat.vhd.

◆ CPLL_REFCLK_SEL_G

CPLL_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 39 of file Pgp2bGth7VarLat.vhd.

◆ CPLL_FBDIV_G

CPLL_FBDIV_G integer := 4
Generic

Definition at line 40 of file Pgp2bGth7VarLat.vhd.

◆ CPLL_FBDIV_45_G

CPLL_FBDIV_45_G integer := 5
Generic

Definition at line 41 of file Pgp2bGth7VarLat.vhd.

◆ CPLL_REFCLK_DIV_G

CPLL_REFCLK_DIV_G integer := 1
Generic

Definition at line 42 of file Pgp2bGth7VarLat.vhd.

◆ RXOUT_DIV_G

RXOUT_DIV_G integer := 2
Generic

Definition at line 43 of file Pgp2bGth7VarLat.vhd.

◆ TXOUT_DIV_G

TXOUT_DIV_G integer := 2
Generic

Definition at line 44 of file Pgp2bGth7VarLat.vhd.

◆ RX_CLK25_DIV_G

RX_CLK25_DIV_G integer := 7
Generic

Definition at line 45 of file Pgp2bGth7VarLat.vhd.

◆ TX_CLK25_DIV_G

TX_CLK25_DIV_G integer := 7
Generic

Definition at line 46 of file Pgp2bGth7VarLat.vhd.

◆ PMA_RSV_G

PMA_RSV_G bit_vector := x " 00000080 "
Generic

Definition at line 48 of file Pgp2bGth7VarLat.vhd.

◆ RX_OS_CFG_G

RX_OS_CFG_G bit_vector := " 0000010000000 "
Generic

Definition at line 49 of file Pgp2bGth7VarLat.vhd.

◆ RXCDR_CFG_G

RXCDR_CFG_G bit_vector := x " 0002007FE1000C2200018 "
Generic

Definition at line 50 of file Pgp2bGth7VarLat.vhd.

◆ RXDFEXYDEN_G

RXDFEXYDEN_G sl := ' 1 '
Generic

Definition at line 51 of file Pgp2bGth7VarLat.vhd.

◆ TX_PLL_G

TX_PLL_G string := " QPLL "
Generic

Definition at line 54 of file Pgp2bGth7VarLat.vhd.

◆ RX_PLL_G

RX_PLL_G string := " CPLL "
Generic

Definition at line 55 of file Pgp2bGth7VarLat.vhd.

◆ TX_BUF_EN_G

TX_BUF_EN_G boolean := true
Generic

Definition at line 58 of file Pgp2bGth7VarLat.vhd.

◆ TX_OUTCLK_SRC_G

TX_OUTCLK_SRC_G string := " OUTCLKPMA "
Generic

Definition at line 59 of file Pgp2bGth7VarLat.vhd.

◆ TX_DLY_BYPASS_G

TX_DLY_BYPASS_G sl := ' 1 '
Generic

Definition at line 60 of file Pgp2bGth7VarLat.vhd.

◆ TX_PHASE_ALIGN_G

TX_PHASE_ALIGN_G string := " NONE "
Generic

Definition at line 61 of file Pgp2bGth7VarLat.vhd.

◆ TX_BUF_ADDR_MODE_G

TX_BUF_ADDR_MODE_G string := " FULL "
Generic

Definition at line 62 of file Pgp2bGth7VarLat.vhd.

◆ VC_INTERLEAVE_G

VC_INTERLEAVE_G integer := 0
Generic

Definition at line 67 of file Pgp2bGth7VarLat.vhd.

◆ PAYLOAD_CNT_TOP_G

PAYLOAD_CNT_TOP_G integer := 7
Generic

Definition at line 68 of file Pgp2bGth7VarLat.vhd.

◆ NUM_VC_EN_G

NUM_VC_EN_G integer range 1 to 4 := 4
Generic

Definition at line 69 of file Pgp2bGth7VarLat.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 70 of file Pgp2bGth7VarLat.vhd.

◆ TX_ENABLE_G

TX_ENABLE_G boolean := true
Generic

Definition at line 71 of file Pgp2bGth7VarLat.vhd.

◆ RX_ENABLE_G

RX_ENABLE_G boolean := true
Generic

Definition at line 72 of file Pgp2bGth7VarLat.vhd.

◆ stableClk

stableClk in sl
Port

Definition at line 75 of file Pgp2bGth7VarLat.vhd.

◆ gtCPllRefClk

gtCPllRefClk in sl
Port

Definition at line 76 of file Pgp2bGth7VarLat.vhd.

◆ gtCPllLock

gtCPllLock out sl
Port

Definition at line 77 of file Pgp2bGth7VarLat.vhd.

◆ gtQPllRefClk

gtQPllRefClk in sl
Port

Definition at line 78 of file Pgp2bGth7VarLat.vhd.

◆ gtQPllClk

gtQPllClk in sl
Port

Definition at line 79 of file Pgp2bGth7VarLat.vhd.

◆ gtQPllLock

gtQPllLock in sl
Port

Definition at line 80 of file Pgp2bGth7VarLat.vhd.

◆ gtQPllRefClkLost

gtQPllRefClkLost in sl
Port

Definition at line 81 of file Pgp2bGth7VarLat.vhd.

◆ gtQPllReset

gtQPllReset out sl
Port

Definition at line 82 of file Pgp2bGth7VarLat.vhd.

◆ gtTxP

gtTxP out sl
Port

Definition at line 84 of file Pgp2bGth7VarLat.vhd.

◆ gtTxN

gtTxN out sl
Port

Definition at line 85 of file Pgp2bGth7VarLat.vhd.

◆ gtRxP

gtRxP in sl
Port

Definition at line 86 of file Pgp2bGth7VarLat.vhd.

◆ gtRxN

gtRxN in sl
Port

Definition at line 87 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxReset

pgpTxReset in sl
Port

Definition at line 89 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxClk

pgpTxClk in sl
Port

Definition at line 90 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxRecClk

pgpTxRecClk out sl
Port

Definition at line 91 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxMmcmReset

pgpTxMmcmReset out sl
Port

Definition at line 92 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxMmcmLocked

pgpTxMmcmLocked in sl
Port

Definition at line 93 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxReset

pgpRxReset in sl
Port

Definition at line 95 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxRecClk

pgpRxRecClk out sl
Port

Definition at line 96 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxClk

pgpRxClk in sl
Port

Definition at line 97 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxMmcmReset

pgpRxMmcmReset out sl
Port

Definition at line 98 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxMmcmLocked

pgpRxMmcmLocked in sl
Port

Definition at line 99 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxIn

pgpRxIn in Pgp2bRxInType
Port

Definition at line 101 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxOut

pgpRxOut out Pgp2bRxOutType
Port

Definition at line 102 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxIn

pgpTxIn in Pgp2bTxInType
Port

Definition at line 104 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxOut

pgpTxOut out Pgp2bTxOutType
Port

Definition at line 105 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxMasters

pgpTxMasters in AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
Port

Definition at line 107 of file Pgp2bGth7VarLat.vhd.

◆ pgpTxSlaves

pgpTxSlaves out AxiStreamSlaveArray ( 3 downto 0 )
Port

Definition at line 108 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxMasters

pgpRxMasters out AxiStreamMasterArray ( 3 downto 0 )
Port

Definition at line 110 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxMasterMuxed

pgpRxMasterMuxed out AxiStreamMasterType
Port

Definition at line 111 of file Pgp2bGth7VarLat.vhd.

◆ pgpRxCtrl

pgpRxCtrl in AxiStreamCtrlArray ( 3 downto 0 )
Port

Definition at line 112 of file Pgp2bGth7VarLat.vhd.

◆ txPreCursor

txPreCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 114 of file Pgp2bGth7VarLat.vhd.

◆ txPostCursor

txPostCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 115 of file Pgp2bGth7VarLat.vhd.

◆ txDiffCtrl

txDiffCtrl in slv ( 3 downto 0 ) := " 1000 "
Port

Definition at line 116 of file Pgp2bGth7VarLat.vhd.

◆ axilClk

axilClk in sl := ' 0 '
Port

Definition at line 118 of file Pgp2bGth7VarLat.vhd.

◆ axilRst

axilRst in sl := ' 0 '
Port

Definition at line 119 of file Pgp2bGth7VarLat.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 120 of file Pgp2bGth7VarLat.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 121 of file Pgp2bGth7VarLat.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 122 of file Pgp2bGth7VarLat.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 123 of file Pgp2bGth7VarLat.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file Pgp2bGth7VarLat.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file Pgp2bGth7VarLat.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file Pgp2bGth7VarLat.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 22 of file Pgp2bGth7VarLat.vhd.

◆ Pgp2bPkg

Pgp2bPkg
Package

Definition at line 23 of file Pgp2bGth7VarLat.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file Pgp2bGth7VarLat.vhd.

The documentation for this class was generated from the following file: