SURF  1.0
PgpGthCoreWrapper.vhd
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1 -------------------------------------------------------------------------------
2 -- File : PgpGthCoreWrapper.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2013-06-29
5 -- Last update: 2016-01-19
6 -------------------------------------------------------------------------------
7 -- Description:
8 -------------------------------------------------------------------------------
9 -- This file is part of 'Example Project Firmware'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'Example Project Firmware', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use work.StdRtlPkg.all;
21 
22 --! @see entity
23  --! @ingroup protocols_pgp_pgp2b_gthUltraScale
25 
26  generic (
27  TPD_G : time := 1 ns);
28 
29  port (
30  stableClk : in sl;
31  stableRst : in sl;
32  -- GTH FPGA IO
33  gtRefClk : in sl;
34  gtRxP : in sl;
35  gtRxN : in sl;
36  gtTxP : out sl;
37  gtTxN : out sl;
38 
39  -- Rx ports
40  rxReset : in sl;
42  rxResetDone : out sl;
43  rxUsrClk : in sl;
44  rxData : out slv(15 downto 0);
45  rxDataK : out slv(1 downto 0);
46  rxDispErr : out slv(1 downto 0);
47  rxDecErr : out slv(1 downto 0);
48  rxPolarity : in sl;
49  rxOutClk : out sl;
50 
51  -- Tx Ports
52  txReset : in sl;
53  txUsrClk : in sl;
55  txResetDone : out sl;
56  txData : in slv(15 downto 0);
57  txDataK : in slv(1 downto 0);
58  txOutClk : out sl;
59 
60  loopback : in slv(2 downto 0));
61 end entity PgpGthCoreWrapper;
62 
63 architecture mapping of PgpGthCoreWrapper is
64 
65  component PgpGthCore
66  port (
67  gtwiz_userclk_tx_active_in : in slv(0 downto 0);
68  gtwiz_userclk_rx_active_in : in slv(0 downto 0);
69  gtwiz_reset_clk_freerun_in : in slv(0 downto 0);
70  gtwiz_reset_all_in : in slv(0 downto 0);
71  gtwiz_reset_tx_pll_and_datapath_in : in slv(0 downto 0);
72  gtwiz_reset_tx_datapath_in : in slv(0 downto 0);
73  gtwiz_reset_rx_pll_and_datapath_in : in slv(0 downto 0);
74  gtwiz_reset_rx_datapath_in : in slv(0 downto 0);
75  gtwiz_reset_rx_cdr_stable_out : out slv(0 downto 0);
76  gtwiz_reset_tx_done_out : out slv(0 downto 0);
77  gtwiz_reset_rx_done_out : out slv(0 downto 0);
78  gtwiz_userdata_tx_in : in slv(15 downto 0);
79  gtwiz_userdata_rx_out : out slv(15 downto 0);
80  drpclk_in : in slv(0 downto 0);
81  gthrxn_in : in slv(0 downto 0);
82  gthrxp_in : in slv(0 downto 0);
83  gtrefclk0_in : in slv(0 downto 0);
84  loopback_in : in slv(2 downto 0);
85  rxbufreset_in : in slv(0 downto 0);
86  rx8b10ben_in : in slv(0 downto 0);
87  rxcommadeten_in : in slv(0 downto 0);
88  rxmcommaalignen_in : in slv(0 downto 0);
89  rxpcommaalignen_in : in slv(0 downto 0);
90  rxpolarity_in : in slv(0 downto 0);
91  rxusrclk_in : in slv(0 downto 0);
92  rxusrclk2_in : in slv(0 downto 0);
93  tx8b10ben_in : in slv(0 downto 0);
94  txctrl0_in : in slv(15 downto 0);
95  txctrl1_in : in slv(15 downto 0);
96  txctrl2_in : in slv(7 downto 0);
97  txusrclk_in : in slv(0 downto 0);
98  txusrclk2_in : in slv(0 downto 0);
99  gthtxn_out : out slv(0 downto 0);
100  gthtxp_out : out slv(0 downto 0);
101  rxbyteisaligned_out : out slv(0 downto 0);
102  rxbyterealign_out : out slv(0 downto 0);
103  rxcommadet_out : out slv(0 downto 0);
104  rxctrl0_out : out slv(15 downto 0);
105  rxctrl1_out : out slv(15 downto 0);
106  rxctrl2_out : out slv(7 downto 0);
107  rxctrl3_out : out slv(7 downto 0);
108  rxoutclk_out : out slv(0 downto 0);
109  rxpmaresetdone_out : out slv(0 downto 0);
110  txoutclk_out : out slv(0 downto 0);
111  txpmaresetdone_out : out slv(0 downto 0)
112  );
113  end component;
114 
115 begin
116 
117  -- Note: Has to be generated from aurora core in order to work properly
118  U_PgpGthCore : PgpGthCore
119  port map (
120  gtwiz_userclk_tx_active_in(0) => txUsrClkActive,
121  gtwiz_userclk_rx_active_in(0) => rxUsrClkActive,
122  gtwiz_reset_clk_freerun_in (0) => stableClk,
123  gtwiz_reset_all_in(0) => stableRst,
124  gtwiz_reset_tx_pll_and_datapath_in(0) => '0',
125  gtwiz_reset_tx_datapath_in(0) => txReset,
126  gtwiz_reset_rx_pll_and_datapath_in(0) => '0',
127  gtwiz_reset_rx_datapath_in(0) => rxReset,
128  gtwiz_reset_rx_cdr_stable_out(0) => open,
129  gtwiz_reset_tx_done_out(0) => txResetDone,
130  gtwiz_reset_rx_done_out(0) => rxResetDone,
131  gtwiz_userdata_tx_in => txData,
132  gtwiz_userdata_rx_out => rxData,
133  drpclk_in(0) => stableClk,
134  gthrxn_in(0) => gtRxN,
135  gthrxp_in(0) => gtRxP,
136  gtrefclk0_in(0) => gtRefClk,
137  loopback_in => loopback,
138  rxbufreset_in(0) => '0',
139  rx8b10ben_in(0) => '1',
140  rxcommadeten_in(0) => '1',
141  rxmcommaalignen_in(0) => '1',
142  rxpcommaalignen_in(0) => '1',
143  rxpolarity_in(0) => rxPolarity,
144  rxusrclk_in(0) => rxUsrClk,
145  rxusrclk2_in(0) => rxUsrClk,
146  tx8b10ben_in(0) => '1',
147  txctrl0_in => X"0000",
148  txctrl1_in => X"0000",
149  txctrl2_in(1 downto 0) => txDataK,
150  txctrl2_in(7 downto 2) => (others => '0'),
151  txusrclk_in(0) => txUsrClk,
152  txusrclk2_in(0) => txUsrClk,
153  gthtxn_out(0) => gtTxN,
154  gthtxp_out(0) => gtTxP,
155  rxbyteisaligned_out(0) => open,
156  rxbyterealign_out(0) => open,
157  rxcommadet_out(0) => open,
158  rxctrl0_out(1 downto 0) => rxDataK,
159  rxctrl0_out(15 downto 2) => open,
160  rxctrl1_out(1 downto 0) => rxDispErr,
161  rxctrl1_out(15 downto 2) => open,
162  rxctrl2_out => open,
163  rxctrl3_out(1 downto 0) => rxDecErr,
164  rxctrl3_out(7 downto 2) => open,
165  rxoutclk_out(0) => rxOutClk,
166  rxpmaresetdone_out(0) => open,
167  txoutclk_out(0) => txOutClk,
168  txpmaresetdone_out(0) => open);
169 end architecture mapping;
out rxDispErrslv( 1 downto 0)
in loopbackslv( 2 downto 0)
std_logic sl
Definition: StdRtlPkg.vhd:28
out rxDecErrslv( 1 downto 0)
in txDataKslv( 1 downto 0)
_library_ ieeeieee
in txDataslv( 15 downto 0)
out rxDataslv( 15 downto 0)
out rxDataKslv( 1 downto 0)
std_logic_vector slv
Definition: StdRtlPkg.vhd:29