SURF  1.0
Gth7QuadPll.vhd
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1 -------------------------------------------------------------------------------
2 -- File : Gth7QuadPll.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-04-01
5 -- Last update: 2016-03-08
6 -------------------------------------------------------------------------------
7 -- Description: Wrapper for Xilinx 7-series GTH's QPLL
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.numeric_std.all;
21 
22 use work.StdRtlPkg.all;
23 use work.AxiLitePkg.all;
24 
25 library unisim;
26 use unisim.vcomponents.all;
27 
28 --! @see entity
29  --! @ingroup xilinx_7Series_gth7
30 entity Gth7QuadPll is
31  generic (
32  TPD_G : time := 1 ns;
33  AXI_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_DECERR_C;
34  SIM_RESET_SPEEDUP_G : string := "TRUE";
35  SIM_VERSION_G : string := "2.0";
36  QPLL_CFG_G : bit_vector := x"04801C7"; -- QPLL_CFG_G[6] selects the QPLL frequency band: 0 = upper band, 1 = lower band
37  QPLL_REFCLK_SEL_G : bit_vector := "001";
38  QPLL_FBDIV_G : bit_vector := "0100100000";
39  QPLL_FBDIV_RATIO_G : bit := '1';
40  QPLL_REFCLK_DIV_G : integer := 1);
41  port (
42  qPllRefClk : in sl;
43  qPllOutClk : out sl;
44  qPllOutRefClk : out sl;
45  qPllLock : out sl;
46  qPllLockDetClk : in sl; -- Lock detect clock
47  qPllRefClkLost : out sl;
48  qPllPowerDown : in sl := '0';
49  qPllReset : in sl;
50  -- AXI-Lite Interface
51  axilClk : in sl := '0';
52  axilRst : in sl := '0';
53  axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
54  axilReadSlave : out AxiLiteReadSlaveType;
55  axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
56  axilWriteSlave : out AxiLiteWriteSlaveType);
57 end entity Gth7QuadPll;
58 
59 architecture mapping of Gth7QuadPll is
60 
61  signal gtRefClk0 : sl;
62  signal gtRefClk1 : sl;
63  signal gtNorthRefClk0 : sl;
64  signal gtNorthRefClk1 : sl;
65  signal gtSouthRefClk0 : sl;
66  signal gtSouthRefClk1 : sl;
67  signal gtGRefClk : sl;
68 
69  signal drpEn : sl;
70  signal drpWe : sl;
71  signal drpRdy : sl;
72  signal drpAddr : slv(7 downto 0);
73  signal drpDi : slv(15 downto 0);
74  signal drpDo : slv(15 downto 0);
75 
76 begin
77 
78  -------------------------------------------------------------------------------
79  -- QPLL clock select. Only ever use 1 clock to drive qpll. Never switch clocks.
80  -------------------------------------------------------------------------------
81  gtRefClk0 <= qpllRefClk when QPLL_REFCLK_SEL_G = "001" else '0';
82  gtRefClk1 <= qpllRefClk when QPLL_REFCLK_SEL_G = "010" else '0';
83  gtNorthRefClk0 <= qpllRefClk when QPLL_REFCLK_SEL_G = "011" else '0';
84  gtNorthRefClk1 <= qpllRefClk when QPLL_REFCLK_SEL_G = "100" else '0';
85  gtSouthRefClk0 <= qpllRefClk when QPLL_REFCLK_SEL_G = "101" else '0';
86  gtSouthRefClk1 <= qpllRefClk when QPLL_REFCLK_SEL_G = "110" else '0';
87  gtGRefClk <= qpllRefClk when QPLL_REFCLK_SEL_G = "111" else '0';
88 
89  gthe2_common_0_i : GTHE2_COMMON
90  generic map (
91  -- Simulation attributes
92  SIM_RESET_SPEEDUP => SIM_RESET_SPEEDUP_G,
93  SIM_QPLLREFCLK_SEL => QPLL_REFCLK_SEL_G,
94  SIM_VERSION => SIM_VERSION_G,
95  ------------------COMMON BLOCK Attributes---------------
96  BIAS_CFG => (x"0000040000001050"),
97  COMMON_CFG => (x"0000001C"),
98  QPLL_CFG => QPLL_CFG_G,
99  QPLL_CLKOUT_CFG => ("1111"),
100  QPLL_COARSE_FREQ_OVRD => ("010000"),
101  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
102  QPLL_CP => ("0000011111"),
103  QPLL_CP_MONITOR_EN => ('0'),
104  QPLL_DMONITOR_SEL => ('0'),
105  QPLL_FBDIV => QPLL_FBDIV_G,
106  QPLL_FBDIV_MONITOR_EN => ('0'),
107  QPLL_FBDIV_RATIO => QPLL_FBDIV_RATIO_G,
108  QPLL_INIT_CFG => (x"000006"),
109  QPLL_LOCK_CFG => (x"05E8"),
110  QPLL_LPF => ("1111"),
111  QPLL_REFCLK_DIV => QPLL_REFCLK_DIV_G,
112  RSVD_ATTR0 => (x"0000"),
113  RSVD_ATTR1 => (x"0000"),
114  QPLL_RP_COMP => ('0'),
115  QPLL_VTRL_RESET => ("00"),
116  RCAL_CFG => ("00"))
117  port map (
118  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
119  DRPADDR => drpAddr,
120  DRPCLK => axilClk,
121  DRPDI => drpDi,
122  DRPDO => drpDo,
123  DRPEN => drpEn,
124  DRPRDY => drpRdy,
125  DRPWE => drpWe,
126  ---------------------- Common Block - Ref Clock Ports ---------------------
127  GTGREFCLK => gtGRefClk,
128  GTNORTHREFCLK0 => gtNorthRefClk0,
129  GTNORTHREFCLK1 => gtNorthRefClk1,
130  GTREFCLK0 => gtRefClk0,
131  GTREFCLK1 => gtRefClk1,
132  GTSOUTHREFCLK0 => gtSouthRefClk0,
133  GTSOUTHREFCLK1 => gtSouthRefClk1,
134  ------------------------- Common Block - QPLL Ports -----------------------
135  QPLLDMONITOR => open,
136  ----------------------- Common Block - Clocking Ports ----------------------
137  QPLLOUTCLK => qPllOutClk,
138  QPLLOUTREFCLK => qPllOutRefClk,
139  REFCLKOUTMONITOR => open,
140  ------------------------- Common Block - QPLL Ports ------------------------
141  BGRCALOVRDENB => '1',
142  PMARSVDOUT => open,
143  QPLLFBCLKLOST => open,
144  QPLLLOCK => qPllLock,
145  QPLLLOCKDETCLK => qPllLockDetClk,
146  QPLLLOCKEN => '1',
147  QPLLOUTRESET => '0',
148  QPLLPD => qPllPowerDown,
149  QPLLREFCLKLOST => qPllRefClkLost,
150  QPLLREFCLKSEL => to_stdlogicvector(QPLL_REFCLK_SEL_G),
151  QPLLRESET => qPllReset,
152  QPLLRSVD1 => "0000000000000000",
153  QPLLRSVD2 => "11111",
154  --------------------------------- QPLL Ports -------------------------------
155  BGBYPASSB => '1',
156  BGMONITORENB => '1',
157  BGPDB => '1',
158  BGRCALOVRD => "00000",
159  PMARSVD => "00000000",
160  RCALENB => '1');
161 
162  U_AxiLiteToDrp : entity work.AxiLiteToDrp
163  generic map (
164  TPD_G => TPD_G,
165  AXI_ERROR_RESP_G => AXI_ERROR_RESP_G,
166  COMMON_CLK_G => true,
167  EN_ARBITRATION_G => false,
168  TIMEOUT_G => 4096,
169  ADDR_WIDTH_G => 8,
170  DATA_WIDTH_G => 16)
171  port map (
172  -- AXI-Lite Port
173  axilClk => axilClk,
174  axilRst => axilRst,
175  axilReadMaster => axilReadMaster,
176  axilReadSlave => axilReadSlave,
177  axilWriteMaster => axilWriteMaster,
178  axilWriteSlave => axilWriteSlave,
179  -- DRP Interface
180  drpClk => axilClk,
181  drpRst => axilRst,
182  drpRdy => drpRdy,
183  drpEn => drpEn,
184  drpWe => drpWe,
185  drpAddr => drpAddr,
186  drpDi => drpDi,
187  drpDo => drpDo);
188 
189 end architecture mapping;
190 
Gth7QuadPll.mapping.drpAddr
slv( 7 downto 0) drpAddr
Definition: Gth7QuadPll.vhd:72
Gth7QuadPll.QPLL_REFCLK_SEL_G
QPLL_REFCLK_SEL_Gbit_vector := "001"
Definition: Gth7QuadPll.vhd:37
AxiLiteToDrp.ADDR_WIDTH_G
ADDR_WIDTH_Gpositive range 1 to 32:= 16
Definition: AxiLiteToDrp.vhd:35
Gth7QuadPll.qPllOutRefClk
out qPllOutRefClksl
Definition: Gth7QuadPll.vhd:44
Gth7QuadPll.qPllRefClk
in qPllRefClksl
Definition: Gth7QuadPll.vhd:42
Gth7QuadPll.QPLL_REFCLK_DIV_G
QPLL_REFCLK_DIV_Ginteger := 1
Definition: Gth7QuadPll.vhd:40
AxiLiteToDrp.drpAddr
out drpAddrslv( ADDR_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:54
Gth7QuadPll.qPllRefClkLost
out qPllRefClkLostsl
Definition: Gth7QuadPll.vhd:47
AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiLiteToDrp.EN_ARBITRATION_G
EN_ARBITRATION_Gboolean := false
Definition: AxiLiteToDrp.vhd:33
Gth7QuadPll.axilRst
in axilRstsl := '0'
Definition: Gth7QuadPll.vhd:52
AxiLiteToDrp.DATA_WIDTH_G
DATA_WIDTH_Gpositive range 1 to 32:= 16
Definition: AxiLiteToDrp.vhd:36
AxiLiteToDrp.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: AxiLiteToDrp.vhd:42
Gth7QuadPll.QPLL_CFG_G
QPLL_CFG_Gbit_vector := x"04801C7"
Definition: Gth7QuadPll.vhd:36
AxiLiteToDrp.drpDo
in drpDoslv( DATA_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:56
AxiLiteToDrp.COMMON_CLK_G
COMMON_CLK_Gboolean := false
Definition: AxiLiteToDrp.vhd:32
Gth7QuadPll.TPD_G
TPD_Gtime := 1 ns
Definition: Gth7QuadPll.vhd:32
Gth7QuadPll.qPllLock
out qPllLocksl
Definition: Gth7QuadPll.vhd:45
Gth7QuadPll.qPllOutClk
out qPllOutClksl
Definition: Gth7QuadPll.vhd:43
Gth7QuadPll.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: Gth7QuadPll.vhd:55
Gth7QuadPll.SIM_RESET_SPEEDUP_G
SIM_RESET_SPEEDUP_Gstring := "TRUE"
Definition: Gth7QuadPll.vhd:34
Gth7Core.ieee
_library_ ieeeieee
Definition: Gth7Core.vhd:18
gthe2_common_0_i
gthe2_common gthe2_common_0_igthe2_common_0_i
Definition: Gth7QuadPll.vhd:160
AxiLiteToDrp.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: AxiLiteToDrp.vhd:44
Gth7QuadPll.mapping.drpDo
slv( 15 downto 0) drpDo
Definition: Gth7QuadPll.vhd:74
Gth7QuadPll.QPLL_FBDIV_RATIO_G
QPLL_FBDIV_RATIO_Gbit := '1'
Definition: Gth7QuadPll.vhd:39
Gth7QuadPll.axilReadMaster
in axilReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: Gth7QuadPll.vhd:53
AxiLitePkg.AXI_RESP_DECERR_C
slv( 1 downto 0) := "11" AXI_RESP_DECERR_C
Definition: AxiLitePkg.vhd:49
Gth7QuadPll.axilClk
in axilClksl := '0'
Definition: Gth7QuadPll.vhd:51
AxiLiteToDrp.axilReadMaster
in axilReadMasterAxiLiteReadMasterType
Definition: AxiLiteToDrp.vhd:41
Gth7QuadPll.qPllReset
in qPllResetsl
Definition: Gth7QuadPll.vhd:49
Gth7QuadPll.SIM_VERSION_G
SIM_VERSION_Gstring := "2.0"
Definition: Gth7QuadPll.vhd:35
Gth7QuadPll.axilReadSlave
out axilReadSlaveAxiLiteReadSlaveType
Definition: Gth7QuadPll.vhd:54
AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59
AxiLiteToDrp.TIMEOUT_G
TIMEOUT_Gpositive := 4096
Definition: AxiLiteToDrp.vhd:34
Gth7QuadPll.qPllPowerDown
in qPllPowerDownsl := '0'
Definition: Gth7QuadPll.vhd:48
AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType :=(araddr =>( others => '0'),arprot =>( others => '0'),arvalid => '0',rready => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69
Gth7QuadPll.qPllLockDetClk
in qPllLockDetClksl
Definition: Gth7QuadPll.vhd:46
Gth7QuadPll.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: Gth7QuadPll.vhd:33
AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85
AxiLiteToDrp.axilWriteMaster
in axilWriteMasterAxiLiteWriteMasterType
Definition: AxiLiteToDrp.vhd:43
Gth7QuadPll.QPLL_FBDIV_G
QPLL_FBDIV_Gbit_vector := "0100100000"
Definition: Gth7QuadPll.vhd:38
AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType :=(awaddr =>( others => '0'),awprot =>( others => '0'),awvalid => '0',wdata =>( others => '0'),wstrb =>( others => '1'),wvalid => '0',bready => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125
AxiLiteToDrp.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_DECERR_C
Definition: AxiLiteToDrp.vhd:31
AxiLiteToDrp.TPD_G
TPD_Gtime := 1 ns
Definition: AxiLiteToDrp.vhd:30
Gth7Core.unisim
_library_ unisimunisim
Definition: Gth7Core.vhd:23
Gth7QuadPll.axilWriteSlave
out axilWriteSlaveAxiLiteWriteSlaveType
Definition: Gth7QuadPll.vhd:56
AxiLiteToDrp.drpDi
out drpDislv( DATA_WIDTH_G- 1 downto 0)
Definition: AxiLiteToDrp.vhd:55
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
Gth7QuadPll.mapping.drpDi
slv( 15 downto 0) drpDi
Definition: Gth7QuadPll.vhd:73