SURF  1.0
Signals | Instantiations
mapping Architecture Reference

Signals

gtRefClk0  sl
gtRefClk1  sl
gtNorthRefClk0  sl
gtNorthRefClk1  sl
gtSouthRefClk0  sl
gtSouthRefClk1  sl
gtGRefClk  sl
drpEn  sl
drpWe  sl
drpRdy  sl
drpAddr  slv ( 7 downto 0 )
drpDi  slv ( 15 downto 0 )
drpDo  slv ( 15 downto 0 )

Instantiations

gthe2_common_0_i  gthe2_common
u_axilitetodrp  AxiLiteToDrp <Entity AxiLiteToDrp>

Detailed Description

Definition at line 59 of file Gth7QuadPll.vhd.

Member Data Documentation

◆ gtRefClk0

gtRefClk0 sl
Signal

Definition at line 61 of file Gth7QuadPll.vhd.

◆ gtRefClk1

gtRefClk1 sl
Signal

Definition at line 62 of file Gth7QuadPll.vhd.

◆ gtNorthRefClk0

gtNorthRefClk0 sl
Signal

Definition at line 63 of file Gth7QuadPll.vhd.

◆ gtNorthRefClk1

gtNorthRefClk1 sl
Signal

Definition at line 64 of file Gth7QuadPll.vhd.

◆ gtSouthRefClk0

gtSouthRefClk0 sl
Signal

Definition at line 65 of file Gth7QuadPll.vhd.

◆ gtSouthRefClk1

gtSouthRefClk1 sl
Signal

Definition at line 66 of file Gth7QuadPll.vhd.

◆ gtGRefClk

gtGRefClk sl
Signal

Definition at line 67 of file Gth7QuadPll.vhd.

◆ drpEn

drpEn sl
Signal

Definition at line 69 of file Gth7QuadPll.vhd.

◆ drpWe

drpWe sl
Signal

Definition at line 70 of file Gth7QuadPll.vhd.

◆ drpRdy

drpRdy sl
Signal

Definition at line 71 of file Gth7QuadPll.vhd.

◆ drpAddr

drpAddr slv ( 7 downto 0 )
Signal

Definition at line 72 of file Gth7QuadPll.vhd.

◆ drpDi

drpDi slv ( 15 downto 0 )
Signal

Definition at line 73 of file Gth7QuadPll.vhd.

◆ drpDo

drpDo slv ( 15 downto 0 )
Signal

Definition at line 74 of file Gth7QuadPll.vhd.

◆ gthe2_common_0_i

gthe2_common_0_i gthe2_common
Instantiation

Definition at line 160 of file Gth7QuadPll.vhd.

◆ u_axilitetodrp

u_axilitetodrp AxiLiteToDrp
Instantiation

Definition at line 187 of file Gth7QuadPll.vhd.

The documentation for this class was generated from the following file: